riscv/rocket-chip
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reset -> resetVal, getReset -> reset

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This commit is contained in:
Huy Vo 2013-08-12 20:52:18 -07:00
parent 5c7a1f5cd6
commit d5c9eb0f54
2 changed files with 3 additions and 3 deletions
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2
uncore/src/llc.scala
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@ -370,7 +370,7 @@ class DRAMSideLLC(sets: Int, ways: Int, outstanding: Int, tagLeaf: Mem[UInt], da
val s3_rdy = Bool() val s3_rdy = Bool()
val replay_s2_rdy = Bool() val replay_s2_rdy = Bool()
val s1_valid = Reg(update = io.cpu.req_cmd.fire() || replay_s2 && replay_s2_rdy, reset = Bool(false)) val s1_valid = Reg(update = io.cpu.req_cmd.fire() || replay_s2 && replay_s2_rdy, resetVal = Bool(false))
val s1 = Reg(new MemReqCmd) val s1 = Reg(new MemReqCmd)
when (io.cpu.req_cmd.fire()) { s1 := io.cpu.req_cmd.bits } when (io.cpu.req_cmd.fire()) { s1 := io.cpu.req_cmd.bits }
when (replay_s2 && replay_s2_rdy) { s1 := s2 } when (replay_s2 && replay_s2_rdy) { s1 := s2 }

4
uncore/src/slowio.scala
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@ -47,7 +47,7 @@ class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module
val out_slow_bits = Reg(data) val out_slow_bits = Reg(data)
val fromhost_q = Module(new Queue(data,1)) val fromhost_q = Module(new Queue(data,1))
fromhost_q.io.enq.valid := rising && (io.in_slow.valid && in_slow_rdy || this.getReset) fromhost_q.io.enq.valid := rising && (io.in_slow.valid && in_slow_rdy || this.reset)
fromhost_q.io.enq.bits := io.in_slow.bits fromhost_q.io.enq.bits := io.in_slow.bits
fromhost_q.io.deq <> io.in_fast fromhost_q.io.deq <> io.in_fast
@ -58,7 +58,7 @@ class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module
when (held) { when (held) {
in_slow_rdy := fromhost_q.io.enq.ready in_slow_rdy := fromhost_q.io.enq.ready
out_slow_val := tohost_q.io.deq.valid out_slow_val := tohost_q.io.deq.valid
out_slow_bits := Mux(this.getReset, fromhost_q.io.deq.bits, tohost_q.io.deq.bits) out_slow_bits := Mux(this.reset, fromhost_q.io.deq.bits, tohost_q.io.deq.bits)
} }
io.in_slow.ready := in_slow_rdy io.in_slow.ready := in_slow_rdy