riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

add configuration checks for TraceGen

Browse Source
This commit is contained in:
Howard Mao 2016-07-20 10:37:10 -07:00
parent 959630630a
commit d56362f04c
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
groundtest/src/main/scala/TraceGen.scala
View File

@ -554,6 +554,9 @@ class TraceGenerator(id: Int)
class GroundTestTraceGenerator(implicit p: Parameters) class GroundTestTraceGenerator(implicit p: Parameters)
extends GroundTest()(p) with HasTraceGenParams { extends GroundTest()(p) with HasTraceGenParams {
require(io.mem.size == 0)
require(io.cache.size == 1)
val traceGen = Module(new TraceGenerator(p(GroundTestId))) val traceGen = Module(new TraceGenerator(p(GroundTestId)))
io.cache.head <> traceGen.io.mem io.cache.head <> traceGen.io.mem