riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

fix AMO replay bug

Browse Source 
didn't check for structural hazard on AMO unit
if a replay was initiated one cycle before before
a hit-under-miss AMO was issued
This commit is contained in:
Andrew Waterman 2012-02-21 01:02:16 -08:00
parent 6135615104
commit d5608b2728
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/nbdcache.scala
View File

@ -913,7 +913,7 @@ class HellaCacheUniproc extends HellaCache with ThreeStateIncoherence {
// replays // replays
val replay = replayer.io.data_req.bits val replay = replayer.io.data_req.bits
val stall_replay = r_replay_amo || p_amo || p_store_valid val stall_replay = r_cpu_req_val && r_req_amo || r_replay_amo || p_amo || p_store_valid
val replay_val = replayer.io.data_req.valid && !stall_replay val replay_val = replayer.io.data_req.valid && !stall_replay
val replay_rdy = data_arb.io.in(1).ready val replay_rdy = data_arb.io.in(1).ready
data_arb.io.in(1).bits.inner_req.offset := replay.offset(offsetmsb,ramindexlsb) data_arb.io.in(1).bits.inner_req.offset := replay.offset(offsetmsb,ramindexlsb)