From d5208466387e11ea4730ab12c1f615b0a70f2949 Mon Sep 17 00:00:00 2001
From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Mon, 18 Aug 2014 19:23:10 -0700
Subject: [PATCH] add README and sbt files

---
 rocket/README.md               | 33 +++++++++++++++++++++++++++++++++
 rocket/build.sbt               |  7 +++++++
 rocket/chisel-dependent.sbt    |  8 ++++++++
 rocket/hardfloat-dependent.sbt |  8 ++++++++
 rocket/uncore-dependent.sbt    |  8 ++++++++
 5 files changed, 64 insertions(+)
 create mode 100644 rocket/README.md
 create mode 100644 rocket/build.sbt
 create mode 100644 rocket/chisel-dependent.sbt
 create mode 100644 rocket/hardfloat-dependent.sbt
 create mode 100644 rocket/uncore-dependent.sbt

diff --git a/rocket/README.md b/rocket/README.md
new file mode 100644
index 00000000..f3257d63
--- /dev/null
+++ b/rocket/README.md
@@ -0,0 +1,33 @@
+Rocket Core Generator
+================================================================
+
+Rocket is a 6-stage single-issue in-order pipeline that executes the 64-bit
+scalar RISC-V ISA.  Rocket implements an MMU that supports page-based virtual
+memory and is able to boot modern operating systems such as Linux.  Rocket
+also has an optional IEEE 754-2008-compliant FPU, which implements both
+single- and double-precision floating-point operations, including fused
+multiply-add.
+
+We plan to open-source our Rocket core generator written in Chisel in the near 
+future.  We are currently in the process of cleaning up the repository.  Please stay tuned.
+
+Currently, a Rocket core with an 8 KB direct-mapped L1 instruction cache
+and an 8 KB direct-mapped L1 data cache has been instantiated and committed to 
+the zynq-fpga infrastructure repository. A copy of the generated Verilog is available
+[here](https://raw.githubusercontent.com/ucb-bar/zynq-fpga/master/hw/src/verilog/Slave.v).
+
+The following table compares a 32-bit ARM Cortex-A5 core to a 64-bit RISC-V
+Rocket core built in the same TSMC process (40GPLUS). Fourth column is the
+ratio of RISC-V Rocket to ARM Cortex-A5. Both use single-instruction-issue,
+in-order pipelines, yet the RISC-V core is faster, smaller, and uses less
+power.
+
+ISA/Implementation | ARM Cortex-A5 | RISC-V Rocket | R/A
+--- | --- | --- | ---
+ISA Register Width | 32 bits | 64 bits | 2
+Frequency | >1 GHz | >1 GHz | 1
+Dhrystone Performance | 1.57 DMIPS/MHz | 1.72 DMIPS/MHz | 1.1
+Area excluding caches | 0.27 mm<sup>2</sup> | 0.14 mm<sup>2</sup> | 0.5
+Area with 16KB caches | 0.53 mm<sup>2</sup> | 0.39 mm<sup>2</sup> | 0.7
+Area Efficiency | 2.96 DMIPS/MHz/mm<sup>2</sup> | 4.41 DMIPS/MHz/mm<sup>2</sup> | 1.5
+Dynamic Power | <0.08 mW/MHz | 0.034 mW/MHz | >= 0.4
diff --git a/rocket/build.sbt b/rocket/build.sbt
new file mode 100644
index 00000000..d9150787
--- /dev/null
+++ b/rocket/build.sbt
@@ -0,0 +1,7 @@
+organization := "edu.berkeley.cs"
+
+version := "1.2"
+
+name := "rocket"
+
+scalaVersion := "2.10.2"
diff --git a/rocket/chisel-dependent.sbt b/rocket/chisel-dependent.sbt
new file mode 100644
index 00000000..e784e5e9
--- /dev/null
+++ b/rocket/chisel-dependent.sbt
@@ -0,0 +1,8 @@
+// Provide a managed dependency on chisel if -DchiselVersion="" is
+// supplied on the command line.
+
+val chiselVersion = System.getProperty("chiselVersion", "None")
+
+libraryDependencies ++= ( if (chiselVersion != "None" ) (
+    "edu.berkeley.cs" %% "chisel" % chiselVersion
+) :: Nil; else Nil)
diff --git a/rocket/hardfloat-dependent.sbt b/rocket/hardfloat-dependent.sbt
new file mode 100644
index 00000000..e6cc8f7e
--- /dev/null
+++ b/rocket/hardfloat-dependent.sbt
@@ -0,0 +1,8 @@
+// Provide a managed dependency on chisel if -DhardfloatVersion="" is
+// supplied on the command line.
+
+val hardfloatVersion = System.getProperty("hardfloatVersion", "None")
+
+libraryDependencies ++= ( if (hardfloatVersion != "None" ) (
+    "edu.berkeley.cs" %% "hardfloat" % hardfloatVersion
+) :: Nil; else Nil)
diff --git a/rocket/uncore-dependent.sbt b/rocket/uncore-dependent.sbt
new file mode 100644
index 00000000..9526f621
--- /dev/null
+++ b/rocket/uncore-dependent.sbt
@@ -0,0 +1,8 @@
+// Provide a managed dependency on chisel if -DuncoreVersion="" is
+// supplied on the command line.
+
+val uncoreVersion = System.getProperty("uncoreVersion", "None")
+
+libraryDependencies ++= ( if (uncoreVersion != "None" ) (
+    "edu.berkeley.cs" %% "uncore" % uncoreVersion
+) :: Nil; else Nil)