From d4a3351cfc6f4d9032d221ac3af3bf38aecfed60 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 25 Mar 2013 23:26:47 -0700 Subject: [PATCH] expose pending interrupts in status register --- rocket/src/main/scala/consts.scala | 2 -- rocket/src/main/scala/ctrl.scala | 8 ++------ rocket/src/main/scala/dpath_util.scala | 6 +++++- 3 files changed, 7 insertions(+), 9 deletions(-) diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index 0c4e2fbe..b6c7fb82 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -54,8 +54,6 @@ trait ScalarOpConstants { trait InterruptConstants { val CAUSE_INTERRUPT = 32 - val IRQ_IPI = 5 - val IRQ_TIMER = 7 } abstract trait RocketDcacheConstants extends uncore.constants.CacheConstants with uncore.constants.AddressConstants { diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index ee90bbe0..664f476c 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -56,8 +56,6 @@ class CtrlDpathIO extends Bundle() val status = new Status().asInput val fp_sboard_clr = Bool(INPUT); val fp_sboard_clra = UFix(INPUT, 5); - val irq_timer = Bool(INPUT); - val irq_ipi = Bool(INPUT); val pcr_replay = Bool(INPUT) } @@ -407,10 +405,8 @@ class Control(implicit conf: RocketConfiguration) extends Component val ctrl_killx = Bool() val ctrl_killm = Bool() - val id_maskable_interrupts = List( - (io.dpath.irq_ipi, IRQ_IPI), - (io.dpath.irq_timer, IRQ_TIMER)) - var id_interrupts = id_maskable_interrupts.map(i => (io.dpath.status.im(i._2) && i._1, UFix(CAUSE_INTERRUPT+i._2))) + val sr = io.dpath.status + var id_interrupts = (0 until sr.ip.getWidth).map(i => (sr.im(i) && sr.ip(i), UFix(CAUSE_INTERRUPT+i))) val (vec_replay, vec_stalld) = if (conf.vec) { // vector control diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index 6086a315..ce8fd4a8 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -55,6 +55,7 @@ class rocketDpathBTB(entries: Int) extends Component } class Status extends Bundle { + val ip = Bits(width = 8) val im = Bits(width = 8) val zero = Bits(width = 7) val vm = Bool() @@ -177,6 +178,8 @@ class PCR(implicit conf: RocketConfiguration) extends Component val wdata = Mux(io.w.en, io.w.data, host_pcr_bits.data) io.status := reg_status + io.status.ip := Cat(r_irq_timer, Bool(false), r_irq_ipi, Bool(false), + Bool(false), Bool(false), Bool(false), Bool(false)) io.ptbr_wen := wen && waddr === PTBR io.evec := Mux(io.exception, reg_ebase, reg_epc).toUFix io.ptbr := reg_ptbr @@ -229,7 +232,7 @@ class PCR(implicit conf: RocketConfiguration) extends Component val read_veccfg = if (conf.vec) Cat(io.vec_nfregs, io.vec_nxregs, io.vec_appvl) else Bits(0) val read_cause = reg_cause(reg_cause.getWidth-1) << conf.xprlen-1 | reg_cause(reg_cause.getWidth-2,0) rdata := AVec[Bits]( - reg_status.toBits, reg_epc, reg_badvaddr, reg_ebase, + io.status.toBits, reg_epc, reg_badvaddr, reg_ebase, reg_count, reg_compare, read_cause, read_ptbr, reg_coreid/*x*/, read_impl/*x*/, reg_coreid, read_impl, reg_k0, reg_k1, reg_k0/*x*/, reg_k1/*x*/, @@ -276,6 +279,7 @@ class PCR(implicit conf: RocketConfiguration) extends Component reg_status.vm := false reg_status.zero := 0 reg_status.im := 0 + reg_status.ip := 0 } }