riscv/rocket-chip
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arbitrate for LLFU writebacks in MEM stage

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This commit is contained in:
Andrew Waterman
2012-02-08 04:21:05 -08:00
parent ebed56500e
commit d471a8b2da
3 changed files with 50 additions and 55 deletions
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5
rocket/src/main/scala/fpu.scala
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@ -92,7 +92,10 @@ class rocketFPUDecoder extends Component
Array(FLW -> List(Y, Y, N, N, N),
FLD -> List(Y, Y, N, N, N),
FSW -> List(Y, N, N, Y, N),
FSD -> List(Y, N, N, Y, N)))
FSD -> List(Y, N, N, Y, N),
MTFSR -> List(Y, N, N, N, N),
MFFSR -> List(Y, N, N, N, N)
))
val valid :: wen :: ren1 :: ren2 :: ren3 :: Nil = decoder
io.valid := valid.toBool