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Merge pull request #785 from freechipsproject/fmul-fix

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Fix FMUL sign of zero
This commit is contained in:
Andrew Waterman
2017-06-06 00:46:03 -07:00
committed by GitHub
parent f0a59a81c8 07ad9203ff
commit d45fc0d670
1 changed files with 1 additions and 2 deletions
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3
src/main/scala/tile/FPU.scala
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@@ -551,9 +551,8 @@ class FPUFMAPipe(val latency: Int, val t: FType)(implicit p: Parameters) extends
val valid = Reg(next=io.in.valid) val valid = Reg(next=io.in.valid)
val in = Reg(new FPInput) val in = Reg(new FPInput)
when (io.in.valid) { when (io.in.valid) {
val signProd = io.in.bits.in1(maxType.sig + maxType.exp) ^ io.in.bits.in2(maxType.sig + maxType.exp)
val one = UInt(1) << (t.sig + t.exp - 1) val one = UInt(1) << (t.sig + t.exp - 1)
val zero = signProd << (t.sig + t.exp) val zero = UInt(1) << (t.sig + t.exp)
val cmd_fma = io.in.bits.ren3 val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23 val cmd_addsub = io.in.bits.swap23
in := io.in.bits in := io.in.bits