riscv/rocket-chip
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Merge branch 'master', remote-tracking branch 'origin' into hwacha

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This commit is contained in:
Yunsup Lee 2013-11-21 14:57:38 -08:00
commit d450b85483
1 changed files with 2 additions and 2 deletions
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rocket/src/main/scala/instructions.scala
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@ -17,7 +17,7 @@ object Instructions
def LUI = Bits("b?????????????????????????0110111") def LUI = Bits("b?????????????????????????0110111")
def AUIPC = Bits("b?????????????????????????0010111") def AUIPC = Bits("b?????????????????????????0010111")
def ADDI = Bits("b?????????????????000?????0010011") def ADDI = Bits("b?????????????????000?????0010011")
def SLLI = Bits("b010000???????????001?????0010011") def SLLI = Bits("b000000???????????001?????0010011")
def SLTI = Bits("b?????????????????010?????0010011") def SLTI = Bits("b?????????????????010?????0010011")
def SLTIU = Bits("b?????????????????011?????0010011") def SLTIU = Bits("b?????????????????011?????0010011")
def XORI = Bits("b?????????????????100?????0010011") def XORI = Bits("b?????????????????100?????0010011")
@ -44,7 +44,7 @@ object Instructions
def REM = Bits("b0000001??????????110?????0110011") def REM = Bits("b0000001??????????110?????0110011")
def REMU = Bits("b0000001??????????111?????0110011") def REMU = Bits("b0000001??????????111?????0110011")
def ADDIW = Bits("b?????????????????000?????0011011") def ADDIW = Bits("b?????????????????000?????0011011")
def SLLIW = Bits("b0100000??????????001?????0011011") def SLLIW = Bits("b0000000??????????001?????0011011")
def SRLIW = Bits("b0000000??????????101?????0011011") def SRLIW = Bits("b0000000??????????101?????0011011")
def SRAIW = Bits("b0100000??????????101?????0011011") def SRAIW = Bits("b0100000??????????101?????0011011")
def ADDW = Bits("b0000000??????????000?????0111011") def ADDW = Bits("b0000000??????????000?????0111011")