From d405ffa949dc556680387afffccb89ba9c1d8644 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 1 May 2013 21:01:20 -0700 Subject: [PATCH] assume all I$ grants bear data --- rocket/src/main/scala/icache.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 9e6ef285..d0437716 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -173,7 +173,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte rdy := state === s_ready && !s2_miss Assert(!c.co.isVoluntary(io.mem.grant.bits.payload) || !io.mem.grant.valid, "UncachedRequestors shouldn't get voluntary grants.") - val (rf_cnt, refill_done) = Counter(io.mem.grant.valid && !c.co.isVoluntary(io.mem.grant.bits.payload), REFILL_CYCLES) + val (rf_cnt, refill_done) = Counter(io.mem.grant.valid, REFILL_CYCLES) val repl_way = if (c.dm) UFix(0) else LFSR16(s2_miss)(log2Up(c.assoc)-1,0) val enc_tagbits = c.code.width(c.tagbits) @@ -225,7 +225,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte for (i <- 0 until c.assoc) { val data_array = Mem(c.sets*REFILL_CYCLES, seqRead = true){ Bits(width = c.code.width(c.databits)) } val s1_raddr = Reg{UFix()} - when (io.mem.grant.valid && c.co.messageHasData(io.mem.grant.bits.payload) && repl_way === UFix(i)) { + when (io.mem.grant.valid && repl_way === UFix(i)) { val d = io.mem.grant.bits.payload.data data_array(Cat(s2_idx,rf_cnt)) := c.code.encode(d) }