riscv/rocket-chip
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Put page homogeneity checker in PMP

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Avoids redundancy between ITLB and DTLB
This commit is contained in:
Andrew Waterman
2017-03-21 12:01:32 -07:00
parent 9e05200e51
commit d3bda9574c
3 changed files with 47 additions and 43 deletions
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14
src/main/scala/rocket/PTW.scala
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@ -7,7 +7,9 @@ import Chisel._
import Chisel.ImplicitConversions._
import config._
import tile._
import coreplex.CacheBlockBytes
import uncore.constants._
import uncore.tilelink2._
import util._
import scala.collection.mutable.ListBuffer
@ -19,6 +21,7 @@ class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
class PTWResp(implicit p: Parameters) extends CoreBundle()(p) {
val pte = new PTE
val level = UInt(width = log2Ceil(pgLevels))
val homogeneous = Bool()
}
class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p)
@ -60,7 +63,7 @@ class PTE(implicit p: Parameters) extends CoreBundle()(p) {
def sx(dummy: Int = 0) = leaf() && x
}
class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
val io = new Bundle {
val requestor = Vec(n, new TLBPTWIO).flip
val mem = new HellaCacheIO
@ -131,11 +134,18 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
io.mem.s1_kill := s1_kill
io.mem.invalidate_lr := Bool(false)
val pmaPgLevelHomogeneous = (0 until pgLevels) map { i =>
TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) * pgLevelBits)))(pte_addr >> pgIdxBits << pgIdxBits).homogeneous
}
val pmaHomogeneous = pmaPgLevelHomogeneous(count)
val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(pte_addr >> pgIdxBits << pgIdxBits, count)
for (i <- 0 until io.requestor.size) {
io.requestor(i).resp.valid := resp_valid(i)
io.requestor(i).resp.bits.pte := r_pte
io.requestor(i).resp.bits.level := count
io.requestor(i).resp.bits.pte.ppn := pte_addr >> pgIdxBits
io.requestor(i).resp.bits.homogeneous := pmpHomogeneous && pmaHomogeneous
io.requestor(i).ptbr := io.dpath.ptbr
io.requestor(i).status := io.dpath.status
io.requestor(i).pmp := io.dpath.pmp
@ -195,6 +205,6 @@ trait CanHavePTW extends HasHellaCache {
trait CanHavePTWModule extends HasHellaCacheModule {
val outer: CanHavePTW
val ptwPorts = ListBuffer(outer.dcache.module.io.ptw)
val ptwOpt = if (outer.usingPTW) { Some(Module(new PTW(outer.nPTWPorts)(outer.p))) } else None
val ptwOpt = if (outer.usingPTW) { Some(Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edgesOut(0), outer.p))) } else None
ptwOpt foreach { ptw => dcachePorts += ptw.io.mem }
}