riscv/rocket-chip
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get local interrupts out of the tile

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Henry Cook
2017-03-29 19:14:04 -07:00
committed by Andrew Waterman
parent 0b9fc94421
commit d3bc99e253
5 changed files with 65 additions and 24 deletions
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2
src/main/scala/rocketchip/BaseTop.scala
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@ -35,7 +35,7 @@ trait HasTopLevelNetworks extends HasPeripheryParameters {
val socBus = LazyModule(new TLXbar) // Wide or unordered-access slave devices (TL-UH)
val peripheryBus = LazyModule(new TLXbar) // Narrow and ordered-access slave devices (TL-UL)
val intBus = LazyModule(new IntXbar) // Interrupts
val intBus = LazyModule(new IntXbar) // Device and global external interrupts
val fsb = LazyModule(new TLBuffer(BufferParams.none)) // Master devices talking to the frontside of the L2
val bsb = LazyModule(new TLBuffer(BufferParams.none)) // Slave devices talking to the backside of the L2
val mem = Seq.fill(nMemoryChannels) { LazyModule(new TLXbar) } // Ports out to DRAM