Minor refactor of StoreGen/AMOALU. Bugfix for 32b ops in L2's AMOALU.
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Henry Cook
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e1f573918d
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123
uncore/src/main/scala/amoalu.scala
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123
uncore/src/main/scala/amoalu.scala
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@ -0,0 +1,123 @@
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// See LICENSE for license details.
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package uncore
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import Chisel._
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abstract class StoreGen(typ: UInt, addr: UInt, dat: UInt) {
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val byte = typ === MT_B || typ === MT_BU
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val half = typ === MT_H || typ === MT_HU
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val word = typ === MT_W || typ === MT_WU
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def mask: UInt
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def data: UInt
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def wordData: UInt
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}
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class StoreGen64(typ: UInt, addr: UInt, dat: UInt) extends StoreGen(typ, addr, dat) {
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def mask =
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Mux(byte, Bits( 1) << addr(2,0),
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Mux(half, Bits( 3) << Cat(addr(2,1), Bits(0,1)),
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Mux(word, Bits( 15) << Cat(addr(2), Bits(0,2)),
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Bits(255))))
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def data =
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Mux(byte, Fill(8, dat( 7,0)),
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Mux(half, Fill(4, dat(15,0)),
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wordData))
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def wordData =
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Mux(word, Fill(2, dat(31,0)),
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dat)
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}
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class StoreGenAligned64(typ: UInt, addr: UInt, dat: UInt) extends StoreGen64(typ, addr, dat) {
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override def data = dat
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override def wordData = dat
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}
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class StoreGen32(typ: UInt, addr: UInt, dat: UInt) extends StoreGen(typ, addr, dat){
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override val word = typ === MT_W
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def mask =
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Mux(byte, Bits( 1) << addr(2,0),
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Mux(half, Bits( 3) << Cat(addr(2,1), Bits(0,1)),
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Bits( 15)))
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def data =
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Mux(byte, Fill(4, dat( 7,0)),
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Mux(half, Fill(2, dat(15,0)),
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wordData))
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def wordData = dat
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def size =
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Mux(byte, UInt("b000"),
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Mux(half, UInt("b001"),
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UInt("b010")))
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}
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class LoadGen64(typ: UInt, addr: UInt, dat: UInt, zero: Bool) {
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val t = new StoreGen64(typ, addr, dat)
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val sign = typ === MT_B || typ === MT_H || typ === MT_W || typ === MT_D
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val wordShift = Mux(addr(2), dat(63,32), dat(31,0))
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val word = Cat(Mux(t.word, Fill(32, sign && wordShift(31)), dat(63,32)), wordShift)
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val halfShift = Mux(addr(1), word(31,16), word(15,0))
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val half = Cat(Mux(t.half, Fill(48, sign && halfShift(15)), word(63,16)), halfShift)
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val byteShift = Mux(zero, UInt(0), Mux(addr(0), half(15,8), half(7,0)))
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val byte = Cat(Mux(zero || t.byte, Fill(56, sign && byteShift(7)), half(63,8)), byteShift)
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}
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class LoadGen32(typ: UInt, addr: UInt, dat: UInt) {
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val t = new StoreGen32(typ, addr, dat)
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val sign = typ === MT_B || typ === MT_H || typ === MT_W
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val word = dat
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val halfShift = Mux(addr(1), word(31,16), word(15,0))
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val half = Cat(Mux(t.half, Fill(16, sign && halfShift(15)), word(31,16)), halfShift)
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val byteShift = Mux(addr(0), half(15,8), half(7,0))
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val byte = Cat(Mux(t.byte, Fill(24, sign && byteShift(7)), half(31,8)), byteShift)
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}
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class AMOALU(rhsIsAligned: Boolean = false)(implicit p: Parameters) extends CacheModule()(p) {
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val operandBits = p(AmoAluOperandBits)
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require(operandBits == 64)
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val io = new Bundle {
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val addr = Bits(INPUT, blockOffBits)
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val cmd = Bits(INPUT, M_SZ)
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val typ = Bits(INPUT, MT_SZ)
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val lhs = Bits(INPUT, operandBits)
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val rhs = Bits(INPUT, operandBits)
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val out = Bits(OUTPUT, operandBits)
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}
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val storegen = if(rhsIsAligned) new StoreGenAligned64(io.typ, io.addr, io.rhs)
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else new StoreGen64(io.typ, io.addr, io.rhs)
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val rhs = storegen.wordData
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val sgned = io.cmd === M_XA_MIN || io.cmd === M_XA_MAX
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val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU
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val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU
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val word = io.typ === MT_W || io.typ === MT_WU || // Logic minimization:
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io.typ === MT_B || io.typ === MT_BU
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val mask = ~UInt(0,64) ^ (io.addr(2) << 31)
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val adder_out = (io.lhs & mask).toUInt + (rhs & mask)
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val cmp_lhs = Mux(word && !io.addr(2), io.lhs(31), io.lhs(63))
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val cmp_rhs = Mux(word && !io.addr(2), rhs(31), rhs(63))
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val lt_lo = io.lhs(31,0) < rhs(31,0)
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val lt_hi = io.lhs(63,32) < rhs(63,32)
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val eq_hi = io.lhs(63,32) === rhs(63,32)
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val lt = Mux(word, Mux(io.addr(2), lt_hi, lt_lo), lt_hi || eq_hi && lt_lo)
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val less = Mux(cmp_lhs === cmp_rhs, lt, Mux(sgned, cmp_lhs, cmp_rhs))
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val out = Mux(io.cmd === M_XA_ADD, adder_out,
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Mux(io.cmd === M_XA_AND, io.lhs & rhs,
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Mux(io.cmd === M_XA_OR, io.lhs | rhs,
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Mux(io.cmd === M_XA_XOR, io.lhs ^ rhs,
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Mux(Mux(less, min, max), io.lhs,
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storegen.data)))))
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val wmask = FillInterleaved(8, storegen.mask)
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io.out := wmask & out | ~wmask & io.lhs
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}
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@ -38,79 +38,6 @@ abstract class CacheModule(implicit val p: Parameters) extends Module
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abstract class CacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasCacheParameters
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class StoreGen(typ: UInt, addr: UInt, dat: UInt) {
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val byte = typ === MT_B || typ === MT_BU
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val half = typ === MT_H || typ === MT_HU
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val word = typ === MT_W || typ === MT_WU
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def mask =
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Mux(byte, Bits( 1) << addr(2,0),
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Mux(half, Bits( 3) << Cat(addr(2,1), Bits(0,1)),
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Mux(word, Bits( 15) << Cat(addr(2), Bits(0,2)),
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Bits(255))))
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def data =
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Mux(byte, Fill(8, dat( 7,0)),
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Mux(half, Fill(4, dat(15,0)),
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wordData))
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lazy val wordData =
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Mux(word, Fill(2, dat(31,0)),
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dat)
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}
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class LoadGen(typ: UInt, addr: UInt, dat: UInt, zero: Bool) {
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val t = new StoreGen(typ, addr, dat)
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val sign = typ === MT_B || typ === MT_H || typ === MT_W || typ === MT_D
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val wordShift = Mux(addr(2), dat(63,32), dat(31,0))
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val word = Cat(Mux(t.word, Fill(32, sign && wordShift(31)), dat(63,32)), wordShift)
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val halfShift = Mux(addr(1), word(31,16), word(15,0))
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val half = Cat(Mux(t.half, Fill(48, sign && halfShift(15)), word(63,16)), halfShift)
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val byteShift = Mux(zero, UInt(0), Mux(addr(0), half(15,8), half(7,0)))
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val byte = Cat(Mux(zero || t.byte, Fill(56, sign && byteShift(7)), half(63,8)), byteShift)
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}
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class AMOALU(implicit p: Parameters) extends CacheModule()(p) {
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val operandBits = p(AmoAluOperandBits)
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require(operandBits == 64)
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val io = new Bundle {
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val addr = Bits(INPUT, blockOffBits)
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val cmd = Bits(INPUT, M_SZ)
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val typ = Bits(INPUT, MT_SZ)
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val lhs = Bits(INPUT, operandBits)
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val rhs = Bits(INPUT, operandBits)
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val out = Bits(OUTPUT, operandBits)
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}
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val storegen = new StoreGen(io.typ, io.addr, io.rhs)
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val rhs = storegen.wordData
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val sgned = io.cmd === M_XA_MIN || io.cmd === M_XA_MAX
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val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU
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val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU
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val word = io.typ === MT_W || io.typ === MT_WU || // Logic minimization:
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io.typ === MT_B || io.typ === MT_BU
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val mask = ~UInt(0,64) ^ (io.addr(2) << 31)
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val adder_out = (io.lhs & mask).toUInt + (rhs & mask)
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val cmp_lhs = Mux(word && !io.addr(2), io.lhs(31), io.lhs(63))
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val cmp_rhs = Mux(word && !io.addr(2), rhs(31), rhs(63))
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val lt_lo = io.lhs(31,0) < rhs(31,0)
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val lt_hi = io.lhs(63,32) < rhs(63,32)
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val eq_hi = io.lhs(63,32) === rhs(63,32)
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val lt = Mux(word, Mux(io.addr(2), lt_hi, lt_lo), lt_hi || eq_hi && lt_lo)
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val less = Mux(cmp_lhs === cmp_rhs, lt, Mux(sgned, cmp_lhs, cmp_rhs))
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val out = Mux(io.cmd === M_XA_ADD, adder_out,
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Mux(io.cmd === M_XA_AND, io.lhs & rhs,
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Mux(io.cmd === M_XA_OR, io.lhs | rhs,
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Mux(io.cmd === M_XA_XOR, io.lhs ^ rhs,
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Mux(Mux(less, min, max), io.lhs,
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storegen.data)))))
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val wmask = FillInterleaved(8, storegen.mask)
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io.out := wmask & out | ~wmask & io.lhs
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}
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abstract class ReplacementPolicy {
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def way: UInt
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def miss: Unit
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@ -652,7 +579,7 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
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// Provide a single ALU per tracker to merge Puts and AMOs with data being
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// refilled, written back, or extant in the cache
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val amoalu = Module(new AMOALU)
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val amoalu = Module(new AMOALU(rhsIsAligned = true))
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amoalu.io.addr := xact.full_addr()
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amoalu.io.cmd := xact.op_code()
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amoalu.io.typ := xact.op_size()
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