diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala
index c45b0578..cdf7e877 100644
--- a/rocket/src/main/scala/btb.scala
+++ b/rocket/src/main/scala/btb.scala
@@ -6,6 +6,7 @@ import Chisel._
 import junctions._
 import cde.{Parameters, Field}
 import Util._
+import uncore.util._
 
 case object BtbKey extends Field[BtbParameters]
 
diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index 5c894c97..51f1e3c1 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -7,6 +7,7 @@ import Util._
 import Instructions._
 import cde.{Parameters, Field}
 import uncore.devices._
+import uncore.util._
 import junctions.AddrMap
 
 class MStatus extends Bundle {
diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index 5c4a27a8..a3ebcc39 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -7,6 +7,7 @@ import Instructions._
 import Util._
 import FPConstants._
 import uncore.constants.MemoryOpConstants._
+import uncore.util._
 import cde.{Parameters, Field}
 
 case object SFMALatency extends Field[Int]
diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala
index 357ad564..9d745cec 100644
--- a/rocket/src/main/scala/ptw.scala
+++ b/rocket/src/main/scala/ptw.scala
@@ -6,6 +6,7 @@ import Chisel._
 import uncore.agents._
 import uncore.constants._
 import Util._
+import uncore.util._
 import cde.{Parameters, Field}
 
 class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
diff --git a/rocket/src/main/scala/rvc.scala b/rocket/src/main/scala/rvc.scala
index b4934408..db4673d2 100644
--- a/rocket/src/main/scala/rvc.scala
+++ b/rocket/src/main/scala/rvc.scala
@@ -4,6 +4,7 @@ import Chisel._
 import Chisel.ImplicitConversions._
 import Util._
 import cde.Parameters
+import uncore.util._
 
 class ExpandedInstruction extends Bundle {
   val bits = UInt(width = 32)
diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala
index e412a34a..5277c660 100644
--- a/rocket/src/main/scala/tlb.scala
+++ b/rocket/src/main/scala/tlb.scala
@@ -9,6 +9,7 @@ import scala.math._
 import cde.{Parameters, Field}
 import uncore.agents.PseudoLRU
 import uncore.coherence._
+import uncore.util._
 
 case object NTLBEntries extends Field[Int]
 
diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala
index 87e0f686..f701dbeb 100644
--- a/rocket/src/main/scala/util.scala
+++ b/rocket/src/main/scala/util.scala
@@ -3,7 +3,7 @@
 package rocket
 
 import Chisel._
-import uncore._
+import uncore.util._
 import scala.math._
 import cde.{Parameters, Field}
 
@@ -29,26 +29,6 @@ object Util {
   implicit def booleanToIntConv(x: Boolean) = new AnyRef {
     def toInt: Int = if (x) 1 else 0
   }
-
-  implicit class SeqToAugmentedSeq[T <: Data](val x: Seq[T]) extends AnyVal {
-    def apply(idx: UInt): T = {
-      if (x.size == 1) {
-        x.head
-      } else {
-        val half = 1 << (log2Ceil(x.size) - 1)
-        val newIdx = idx & (half - 1)
-        Mux(idx >= UInt(half), x.drop(half)(newIdx), x.take(half)(newIdx))
-      }
-    }
-
-    def asUInt(): UInt = Cat(x.map(_.asUInt).reverse)
-  }
-
-  implicit class UIntIsOneOf(val x: UInt) extends AnyVal {
-    def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).reduce(_||_)
-
-    def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
-  }
 }
 
 import Util._