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Debug Controls (#639)

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* debug: Bump OpenOCD version to one that drives resets and sets cmderr appropriately.

* debug: Export the dmactive and ndreset signals to the top level and drive reset as intended in the TestHarness.
This commit is contained in:
Megan Wachs
2017-04-03 13:31:35 -07:00
committed by GitHub
parent 716533f77f
commit d2c1bdc2ce
5 changed files with 17 additions and 8 deletions
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6
src/main/scala/uncore/devices/debug/Debug.scala
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@ -215,7 +215,7 @@ class DebugInternalBundle ()(implicit val p: Parameters) extends ParameterizedBu
class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) {
val debugUnavail = Vec(nComponents, Bool()).asInput
val ndreset = Bool(OUTPUT)
val debugActive = Bool(OUTPUT)
val dmactive = Bool(OUTPUT)
}
//*****************************************
@ -404,7 +404,7 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
io.innerCtrl.bits.resumereq := DMCONTROLWrData.resumereq
io.ctrl.ndreset := DMCONTROLReg.ndmreset
io.ctrl.debugActive := DMCONTROLReg.dmactive
io.ctrl.dmactive := DMCONTROLReg.dmactive
}
}
@ -1109,7 +1109,7 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule {
dmOuter.module.clock := io.dmi.dmiClock
dmInner.module.io.innerCtrl := dmOuter.module.io.innerCtrl
dmInner.module.io.dmactive := dmOuter.module.io.ctrl.debugActive
dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive
dmInner.module.io.debugUnavail := io.ctrl.debugUnavail
io.ctrl <> dmOuter.module.io.ctrl