Debug Controls (#639)

* debug: Bump OpenOCD version to one that drives resets and sets cmderr appropriately.

* debug: Export the dmactive and ndreset signals to the top level and drive reset as intended in the TestHarness.

src/main/scala/rocketchip/RISCVPlatform.scala

@@ -80,6 +80,8 @@ trait PeripheryDebugBundle extends HasTopLevelNetworksBundle {
   val jtag        = (p(IncludeJtagDTM)).option(new JTAGIO(hasTRSTn = false).flip)
   val jtag_reset  = (p(IncludeJtagDTM)).option(Bool(INPUT))
 
+  val ndreset = Bool(OUTPUT)
+  val dmactive = Bool(OUTPUT)
 }
 
 trait PeripheryDebugModule extends HasTopLevelNetworksModule {
@@ -100,6 +102,10 @@ trait PeripheryDebugModule extends HasTopLevelNetworksModule {
     outer.coreplex.module.io.debug.dmiClock := io.jtag.get.TCK
     outer.coreplex.module.io.debug.dmiReset := ResetCatchAndSync(io.jtag.get.TCK, io.jtag_reset.get, "dmiResetCatch")
   }
+
+  io.ndreset  := outer.coreplex.module.io.ndreset
+  io.dmactive := outer.coreplex.module.io.dmactive
+
 }
 
 /// Real-time clock is based on RTCPeriod relative to Top clock

src/main/scala/rocketchip/TestHarness.scala

@@ -14,7 +14,10 @@ class TestHarness()(implicit p: Parameters) extends Module {
   val io = new Bundle {
     val success = Bool(OUTPUT)
   }
+
   val dut = Module(LazyModule(new ExampleRocketTop).module)
+  dut.reset := reset | dut.io.ndreset
+
 
   dut.io.interrupts := UInt(0)