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Debug Controls (#639)

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* debug: Bump OpenOCD version to one that drives resets and sets cmderr appropriately.

* debug: Export the dmactive and ndreset signals to the top level and drive reset as intended in the TestHarness.
This commit is contained in:
Megan Wachs
2017-04-03 13:31:35 -07:00
committed by GitHub
parent 716533f77f
commit d2c1bdc2ce
5 changed files with 17 additions and 8 deletions
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8
src/main/scala/coreplex/RISCVPlatform.scala
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@ -37,6 +37,8 @@ trait CoreplexRISCVPlatformBundle extends CoreplexNetworkBundle {
val debug = new ClockedDMIIO().flip
val rtcToggle = Bool(INPUT)
val resetVector = UInt(INPUT, p(XLen))
val ndreset = Bool(OUTPUT)
val dmactive = Bool(OUTPUT)
}
trait CoreplexRISCVPlatformModule extends CoreplexNetworkModule {
@ -47,10 +49,8 @@ trait CoreplexRISCVPlatformModule extends CoreplexNetworkModule {
// TODO in inheriting traits: Set this to something meaningful, e.g. "component is in reset or powered down"
val nDebugComponents = outer.debug.intnode.bundleOut.size
outer.debug.module.io.ctrl.debugUnavail := Vec.fill(nDebugComponents){Bool(false)}
// TODO in inheriting traits: Use these values in your power and reset controls.
// TODO Or move these signals to Coreplex Top Level
// ... := outer.debug.module.io.ctrl.dmactive
// ... := outer.debug.module.io.ctrl.ndreset
io.dmactive := outer.debug.module.io.ctrl.dmactive
io.ndreset := outer.debug.module.io.ctrl.ndreset
// Synchronize the rtc into the coreplex
val rtcSync = ShiftRegister(io.rtcToggle, 3)