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diplomacy: require masters to have a name

This commit is contained in:
Wesley W. Terpstra 2017-06-02 15:09:35 -07:00
parent 475ac93cdf
commit d25ad10592
20 changed files with 35 additions and 20 deletions

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@ -154,13 +154,16 @@ abstract class HellaCache(implicit p: Parameters) extends LazyModule {
val node = TLClientNode(Seq(TLClientPortParameters( val node = TLClientNode(Seq(TLClientPortParameters(
clients = cfg.scratch.map { _ => Seq( clients = cfg.scratch.map { _ => Seq(
TLClientParameters( TLClientParameters(
name = s"Core xx DCache MMIO",
sourceId = IdRange(0, cfg.nMMIOs), sourceId = IdRange(0, cfg.nMMIOs),
requestFifo = true)) requestFifo = true))
} getOrElse { Seq( } getOrElse { Seq(
TLClientParameters( TLClientParameters(
name = s"Core xx DCache MMIO",
sourceId = IdRange(0, firstMMIO), sourceId = IdRange(0, firstMMIO),
supportsProbe = TransferSizes(1, cfg.blockBytes)), supportsProbe = TransferSizes(1, cfg.blockBytes)),
TLClientParameters( TLClientParameters(
name = s"Core xx DCache",
sourceId = IdRange(firstMMIO, firstMMIO+cfg.nMMIOs), sourceId = IdRange(firstMMIO, firstMMIO+cfg.nMMIOs),
requestFifo = true)) requestFifo = true))
}, },

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@ -36,7 +36,7 @@ class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICache
class ICache(val latency: Int, val hartid: Int)(implicit p: Parameters) extends LazyModule class ICache(val latency: Int, val hartid: Int)(implicit p: Parameters) extends LazyModule
with HasRocketCoreParameters { with HasRocketCoreParameters {
lazy val module = new ICacheModule(this) lazy val module = new ICacheModule(this)
val masterNode = TLClientNode(TLClientParameters(sourceId = IdRange(0,1))) val masterNode = TLClientNode(TLClientParameters(name = s"Core ${hartid} ICache"))
val icacheParams = tileParams.icache.get val icacheParams = tileParams.icache.get
val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes

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@ -241,6 +241,7 @@ trait PeripherySlaveAXI4 extends HasTopLevelNetworks {
private val config = p(ExtIn) private val config = p(ExtIn)
val l2FrontendAXI4Node = AXI4BlindInputNode(Seq(AXI4MasterPortParameters( val l2FrontendAXI4Node = AXI4BlindInputNode(Seq(AXI4MasterPortParameters(
masters = Seq(AXI4MasterParameters( masters = Seq(AXI4MasterParameters(
name = "AXI4 periphery",
id = IdRange(0, 1 << config.idBits)))))) id = IdRange(0, 1 << config.idBits))))))
private val fifoBits = 1 private val fifoBits = 1
@ -311,6 +312,7 @@ trait PeripherySlaveTL extends HasTopLevelNetworks {
private val config = p(ExtIn) private val config = p(ExtIn)
val l2FrontendTLNode = TLBlindInputNode(Seq(TLClientPortParameters( val l2FrontendTLNode = TLBlindInputNode(Seq(TLClientPortParameters(
clients = Seq(TLClientParameters( clients = Seq(TLClientParameters(
name = "TL periph",
sourceId = IdRange(0, 1 << config.idBits)))))) sourceId = IdRange(0, 1 << config.idBits))))))
fsb.node := fsb.node :=

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@ -49,7 +49,9 @@ class SimAXIMem(channels: Int, forceSize: BigInt = 0)(implicit p: Parameters) ex
require(totalSize % channels == 0) require(totalSize % channels == 0)
val node = AXI4BlindInputNode(Seq.fill(channels) { val node = AXI4BlindInputNode(Seq.fill(channels) {
AXI4MasterPortParameters(Seq(AXI4MasterParameters(IdRange(0, 1 << config.idBits))))}) AXI4MasterPortParameters(Seq(AXI4MasterParameters(
name = "dut",
id = IdRange(0, 1 << config.idBits))))})
for (i <- 0 until channels) { for (i <- 0 until channels) {
val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = config.beatBytes)) val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = config.beatBytes))

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@ -52,10 +52,8 @@ case class AHBSlavePortParameters(
} }
case class AHBMasterParameters( case class AHBMasterParameters(
name: String,
nodePath: Seq[BaseNode] = Seq()) nodePath: Seq[BaseNode] = Seq())
{
val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
}
case class AHBMasterPortParameters( case class AHBMasterPortParameters(
masters: Seq[AHBMasterParameters]) masters: Seq[AHBMasterParameters])

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@ -11,7 +11,7 @@ import uncore.tilelink2._
case class AHBToTLNode() extends MixedAdapterNode(AHBImp, TLImp)( case class AHBToTLNode() extends MixedAdapterNode(AHBImp, TLImp)(
dFn = { case AHBMasterPortParameters(masters) => dFn = { case AHBMasterPortParameters(masters) =>
TLClientPortParameters(clients = masters.map { m => TLClientPortParameters(clients = masters.map { m =>
TLClientParameters(nodePath = m.nodePath) TLClientParameters(name = m.name, nodePath = m.nodePath)
}) })
}, },
uFn = { mp => AHBSlavePortParameters( uFn = { mp => AHBSlavePortParameters(

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@ -42,10 +42,8 @@ case class APBSlavePortParameters(
} }
case class APBMasterParameters( case class APBMasterParameters(
name: String,
nodePath: Seq[BaseNode] = Seq()) nodePath: Seq[BaseNode] = Seq())
{
val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
}
case class APBMasterPortParameters( case class APBMasterPortParameters(
masters: Seq[APBMasterParameters]) masters: Seq[APBMasterParameters])

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@ -16,15 +16,19 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
masterFn = { mp => masterFn = { mp =>
// Create one new "master" per ID // Create one new "master" per ID
val masters = Array.tabulate(1 << idBits) { i => AXI4MasterParameters( val masters = Array.tabulate(1 << idBits) { i => AXI4MasterParameters(
name = "",
id = IdRange(i, i+1), id = IdRange(i, i+1),
aligned = true, aligned = true,
maxFlight = Some(0)) maxFlight = Some(0))
} }
// Accumluate the names of masters we squish
val names = Array.fill(1 << idBits) { new scala.collection.mutable.HashSet[String]() }
// Squash the information from original masters into new ID masters // Squash the information from original masters into new ID masters
mp.masters.foreach { m => mp.masters.foreach { m =>
for (i <- m.id.start until m.id.end) { for (i <- m.id.start until m.id.end) {
val j = i % (1 << idBits) val j = i % (1 << idBits)
val old = masters(j) val old = masters(j)
names(j) += m.name
masters(j) = old.copy( masters(j) = old.copy(
aligned = old.aligned && m.aligned, aligned = old.aligned && m.aligned,
maxFlight = old.maxFlight.flatMap { o => m.maxFlight.map { n => o+n } }) maxFlight = old.maxFlight.flatMap { o => m.maxFlight.map { n => o+n } })
@ -32,7 +36,7 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
} }
mp.copy( mp.copy(
userBits = mp.userBits + max(0, log2Ceil(mp.endId) - idBits), userBits = mp.userBits + max(0, log2Ceil(mp.endId) - idBits),
masters = masters) masters = masters.zipWithIndex.map { case (m,i) => m.copy(name = names(i).toList.mkString(", "))})
}, },
slaveFn = { sp => sp slaveFn = { sp => sp
}) })

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@ -58,12 +58,12 @@ case class AXI4SlavePortParameters(
} }
case class AXI4MasterParameters( case class AXI4MasterParameters(
name: String,
id: IdRange = IdRange(0, 1), id: IdRange = IdRange(0, 1),
aligned: Boolean = false, aligned: Boolean = false,
maxFlight: Option[Int] = None, // None = infinite, else is a per-ID cap maxFlight: Option[Int] = None, // None = infinite, else is a per-ID cap
nodePath: Seq[BaseNode] = Seq()) nodePath: Seq[BaseNode] = Seq())
{ {
val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
maxFlight.foreach { m => require (m >= 0) } maxFlight.foreach { m => require (m >= 0) }
} }

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@ -16,6 +16,7 @@ case class AXI4ToTLNode() extends MixedAdapterNode(AXI4Imp, TLImp)(
clients = masters.flatMap { m => clients = masters.flatMap { m =>
for (id <- m.id.start until m.id.end) for (id <- m.id.start until m.id.end)
yield TLClientParameters( yield TLClientParameters(
name = s"${m.name} ID#${id}",
sourceId = IdRange(id * maxFlight*2, (id+1) * maxFlight*2), // R+W ids are distinct sourceId = IdRange(id * maxFlight*2, (id+1) * maxFlight*2), // R+W ids are distinct
nodePath = m.nodePath, nodePath = m.nodePath,
requestFifo = true) requestFifo = true)

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@ -1093,7 +1093,7 @@ class ClockedDMIIO(implicit val p: Parameters) extends ParameterizedBundle()(p){
class DMIToTL(implicit p: Parameters) extends LazyModule { class DMIToTL(implicit p: Parameters) extends LazyModule {
val node = TLClientNode(TLClientParameters()) val node = TLClientNode(TLClientParameters("debug"))
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {
val io = new Bundle { val io = new Bundle {

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@ -15,6 +15,7 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa
val node = TLAdapterNode( val node = TLAdapterNode(
clientFn = { cp => clientFn = { cp =>
cp.copy(clients = Seq(TLClientParameters( cp.copy(clients = Seq(TLClientParameters(
name = "TLBroadcast",
sourceId = IdRange(0, 1 << log2Ceil(cp.endSourceId*4))))) sourceId = IdRange(0, 1 << log2Ceil(cp.endSourceId*4)))))
}, },
managerFn = { mp => managerFn = { mp =>

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@ -46,6 +46,7 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
// We require that all the responses are mutually FIFO // We require that all the responses are mutually FIFO
// Thus we need to compact all of the masters into one big master // Thus we need to compact all of the masters into one big master
clientFn = { c => c.copy(clients = Seq(TLClientParameters( clientFn = { c => c.copy(clients = Seq(TLClientParameters(
name = "TLFragmenter",
sourceId = IdRange(0, c.endSourceId << addedBits), sourceId = IdRange(0, c.endSourceId << addedBits),
requestFifo = true))) }, requestFifo = true))) },
managerFn = { m => m.copy(managers = m.managers.map(mapManager)) }) managerFn = { m => m.copy(managers = m.managers.map(mapManager)) })

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@ -85,7 +85,9 @@ class TLFuzzer(
noModify: Boolean = false, noModify: Boolean = false,
overrideAddress: Option[AddressSet] = None)(implicit p: Parameters) extends LazyModule overrideAddress: Option[AddressSet] = None)(implicit p: Parameters) extends LazyModule
{ {
val node = TLClientNode(TLClientParameters(sourceId = IdRange(0,inFlight))) val node = TLClientNode(TLClientParameters(
name = "Fuzzer",
sourceId = IdRange(0,inFlight)))
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {
val io = new Bundle { val io = new Bundle {

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@ -12,6 +12,7 @@ class TLLegacy(implicit p: Parameters) extends LazyModule with HasTileLinkParame
{ {
// TL legacy clients don't support anything fancy // TL legacy clients don't support anything fancy
val node = TLClientNode(TLClientParameters( val node = TLClientNode(TLClientParameters(
name = "TLLegacy",
sourceId = IdRange(0, 1 << tlClientXactIdBits))) sourceId = IdRange(0, 1 << tlClientXactIdBits)))
lazy val module = new LazyModuleImp(this) with HasTileLinkParameters { lazy val module = new LazyModuleImp(this) with HasTileLinkParameters {

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@ -167,6 +167,7 @@ case class TLManagerPortParameters(
} }
case class TLClientParameters( case class TLClientParameters(
name: String,
sourceId: IdRange = IdRange(0,1), sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(), nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false, // only a request, not a requirement requestFifo: Boolean = false, // only a request, not a requirement
@ -197,8 +198,6 @@ case class TLClientParameters(
supportsGet.max, supportsGet.max,
supportsPutFull.max, supportsPutFull.max,
supportsPutPartial.max).max supportsPutPartial.max).max
val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
} }
case class TLClientPortParameters( case class TLClientPortParameters(

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@ -14,7 +14,9 @@ class TLSourceShrinker(maxInFlight: Int)(implicit p: Parameters) extends LazyMod
require (maxInFlight > 0) require (maxInFlight > 0)
// The SourceShrinker completely destroys all FIFO property guarantees // The SourceShrinker completely destroys all FIFO property guarantees
private val client = TLClientParameters(sourceId = IdRange(0, maxInFlight)) private val client = TLClientParameters(
name = "TLSourceShrinker",
sourceId = IdRange(0, maxInFlight))
val node = TLAdapterNode( val node = TLAdapterNode(
// We erase all client information since we crush the source Ids // We erase all client information since we crush the source Ids
clientFn = { _ => TLClientPortParameters(clients = Seq(client)) }, clientFn = { _ => TLClientPortParameters(clients = Seq(client)) },

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@ -12,7 +12,7 @@ import AHBParameters._
case class TLToAHBNode() extends MixedAdapterNode(TLImp, AHBImp)( case class TLToAHBNode() extends MixedAdapterNode(TLImp, AHBImp)(
dFn = { case TLClientPortParameters(clients, unsafeAtomics, minLatency) => dFn = { case TLClientPortParameters(clients, unsafeAtomics, minLatency) =>
val masters = clients.map { case c => AHBMasterParameters(nodePath = c.nodePath) } val masters = clients.map { case c => AHBMasterParameters(name = c.name, nodePath = c.nodePath) }
AHBMasterPortParameters(masters) AHBMasterPortParameters(masters)
}, },
uFn = { case AHBSlavePortParameters(slaves, beatBytes) => uFn = { case AHBSlavePortParameters(slaves, beatBytes) =>

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@ -12,7 +12,7 @@ import APBParameters._
case class TLToAPBNode() extends MixedAdapterNode(TLImp, APBImp)( case class TLToAPBNode() extends MixedAdapterNode(TLImp, APBImp)(
dFn = { case TLClientPortParameters(clients, unsafeAtomics, minLatency) => dFn = { case TLClientPortParameters(clients, unsafeAtomics, minLatency) =>
val masters = clients.map { case c => APBMasterParameters(nodePath = c.nodePath) } val masters = clients.map { case c => APBMasterParameters(name = c.name, nodePath = c.nodePath) }
APBMasterPortParameters(masters) APBMasterPortParameters(masters)
}, },
uFn = { case APBSlavePortParameters(slaves, beatBytes) => uFn = { case APBSlavePortParameters(slaves, beatBytes) =>

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@ -17,6 +17,7 @@ case class TLToAXI4Node(beatBytes: Int) extends MixedAdapterNode(TLImp, AXI4Imp)
val idStart = idSize.scanLeft(0)(_+_).init val idStart = idSize.scanLeft(0)(_+_).init
val masters = ((idStart zip idSize) zip clients) map { case ((start, size), c) => val masters = ((idStart zip idSize) zip clients) map { case ((start, size), c) =>
AXI4MasterParameters( AXI4MasterParameters(
name = c.name,
id = IdRange(start, start+size), id = IdRange(start, start+size),
aligned = true, aligned = true,
maxFlight = Some(if (c.requestFifo) c.sourceId.size else 1), maxFlight = Some(if (c.requestFifo) c.sourceId.size else 1),