diplomacy: require masters to have a name

src/main/scala/uncore/tilelink2/Broadcast.scala

@@ -15,6 +15,7 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa
   val node = TLAdapterNode(
     clientFn  = { cp =>
       cp.copy(clients = Seq(TLClientParameters(
+        name     = "TLBroadcast",
         sourceId = IdRange(0, 1 << log2Ceil(cp.endSourceId*4)))))
     },
     managerFn = { mp =>

src/main/scala/uncore/tilelink2/Fragmenter.scala

@@ -46,7 +46,8 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
     // We require that all the responses are mutually FIFO
     // Thus we need to compact all of the masters into one big master
     clientFn  = { c => c.copy(clients = Seq(TLClientParameters(
-      sourceId = IdRange(0, c.endSourceId << addedBits),
+      name        = "TLFragmenter",
+      sourceId    = IdRange(0, c.endSourceId << addedBits),
       requestFifo = true))) },
     managerFn = { m => m.copy(managers = m.managers.map(mapManager)) })
 

src/main/scala/uncore/tilelink2/Fuzzer.scala

@@ -85,7 +85,9 @@ class TLFuzzer(
     noModify: Boolean = false,
     overrideAddress: Option[AddressSet] = None)(implicit p: Parameters) extends LazyModule
 {
-  val node = TLClientNode(TLClientParameters(sourceId = IdRange(0,inFlight)))
+  val node = TLClientNode(TLClientParameters(
+    name = "Fuzzer",
+    sourceId = IdRange(0,inFlight)))
 
   lazy val module = new LazyModuleImp(this) {
     val io = new Bundle {

src/main/scala/uncore/tilelink2/Legacy.scala

@@ -12,6 +12,7 @@ class TLLegacy(implicit p: Parameters) extends LazyModule with HasTileLinkParame
 {
   // TL legacy clients don't support anything fancy
   val node = TLClientNode(TLClientParameters(
+    name     = "TLLegacy",
     sourceId = IdRange(0, 1 << tlClientXactIdBits)))
 
   lazy val module = new LazyModuleImp(this) with HasTileLinkParameters {

src/main/scala/uncore/tilelink2/Parameters.scala

@@ -167,6 +167,7 @@ case class TLManagerPortParameters(
 }
 
 case class TLClientParameters(
+  name:                String,
   sourceId:            IdRange       = IdRange(0,1),
   nodePath:            Seq[BaseNode] = Seq(),
   requestFifo:         Boolean       = false, // only a request, not a requirement
@@ -197,8 +198,6 @@ case class TLClientParameters(
     supportsGet.max,
     supportsPutFull.max,
     supportsPutPartial.max).max
-
-  val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
 }
 
 case class TLClientPortParameters(

src/main/scala/uncore/tilelink2/SourceShrinker.scala

@@ -14,7 +14,9 @@ class TLSourceShrinker(maxInFlight: Int)(implicit p: Parameters) extends LazyMod
   require (maxInFlight > 0)
 
   // The SourceShrinker completely destroys all FIFO property guarantees
-  private val client = TLClientParameters(sourceId = IdRange(0, maxInFlight))
+  private val client = TLClientParameters(
+    name     = "TLSourceShrinker",
+    sourceId = IdRange(0, maxInFlight))
   val node = TLAdapterNode(
     // We erase all client information since we crush the source Ids
     clientFn  = { _ => TLClientPortParameters(clients = Seq(client)) },

src/main/scala/uncore/tilelink2/ToAHB.scala

@@ -12,7 +12,7 @@ import AHBParameters._
 
 case class TLToAHBNode() extends MixedAdapterNode(TLImp, AHBImp)(
   dFn = { case TLClientPortParameters(clients, unsafeAtomics, minLatency) =>
-    val masters = clients.map { case c => AHBMasterParameters(nodePath = c.nodePath) }
+    val masters = clients.map { case c => AHBMasterParameters(name = c.name, nodePath = c.nodePath) }
     AHBMasterPortParameters(masters)
   },
   uFn = { case AHBSlavePortParameters(slaves, beatBytes) =>

src/main/scala/uncore/tilelink2/ToAPB.scala

@@ -12,7 +12,7 @@ import APBParameters._
 
 case class TLToAPBNode() extends MixedAdapterNode(TLImp, APBImp)(
   dFn = { case TLClientPortParameters(clients, unsafeAtomics, minLatency) =>
-    val masters = clients.map { case c => APBMasterParameters(nodePath = c.nodePath) }
+    val masters = clients.map { case c => APBMasterParameters(name = c.name, nodePath = c.nodePath) }
     APBMasterPortParameters(masters)
   },
   uFn = { case APBSlavePortParameters(slaves, beatBytes) =>

src/main/scala/uncore/tilelink2/ToAXI4.scala

@@ -17,6 +17,7 @@ case class TLToAXI4Node(beatBytes: Int) extends MixedAdapterNode(TLImp, AXI4Imp)
     val idStart = idSize.scanLeft(0)(_+_).init
     val masters = ((idStart zip idSize) zip clients) map { case ((start, size), c) =>
       AXI4MasterParameters(
+        name      = c.name,
         id        = IdRange(start, start+size),
         aligned   = true,
         maxFlight = Some(if (c.requestFifo) c.sourceId.size else 1),