riscv/rocket-chip
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diplomacy: require masters to have a name

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This commit is contained in:
Wesley W. Terpstra
2017-06-02 15:09:35 -07:00
parent 475ac93cdf
commit d25ad10592
20 changed files with 35 additions and 20 deletions
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4
src/main/scala/rocketchip/Periphery.scala
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@ -241,7 +241,8 @@ trait PeripherySlaveAXI4 extends HasTopLevelNetworks {
private val config = p(ExtIn)
val l2FrontendAXI4Node = AXI4BlindInputNode(Seq(AXI4MasterPortParameters(
masters = Seq(AXI4MasterParameters(
id = IdRange(0, 1 << config.idBits))))))
name = "AXI4 periphery",
id = IdRange(0, 1 << config.idBits))))))
private val fifoBits = 1
fsb.node :=
@ -311,6 +312,7 @@ trait PeripherySlaveTL extends HasTopLevelNetworks {
private val config = p(ExtIn)
val l2FrontendTLNode = TLBlindInputNode(Seq(TLClientPortParameters(
clients = Seq(TLClientParameters(
name = "TL periph",
sourceId = IdRange(0, 1 << config.idBits))))))
fsb.node :=

4
src/main/scala/rocketchip/TestHarness.scala
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@ -49,7 +49,9 @@ class SimAXIMem(channels: Int, forceSize: BigInt = 0)(implicit p: Parameters) ex
require(totalSize % channels == 0)
val node = AXI4BlindInputNode(Seq.fill(channels) {
AXI4MasterPortParameters(Seq(AXI4MasterParameters(IdRange(0, 1 << config.idBits))))})
AXI4MasterPortParameters(Seq(AXI4MasterParameters(
name = "dut",
id = IdRange(0, 1 << config.idBits))))})
for (i <- 0 until channels) {
val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = config.beatBytes))