riscv/rocket-chip
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diplomacy: require masters to have a name

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This commit is contained in:
Wesley W. Terpstra
2017-06-02 15:09:35 -07:00
parent 475ac93cdf
commit d25ad10592
20 changed files with 35 additions and 20 deletions
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3
src/main/scala/rocket/HellaCache.scala
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@ -154,13 +154,16 @@ abstract class HellaCache(implicit p: Parameters) extends LazyModule {
val node = TLClientNode(Seq(TLClientPortParameters(
clients = cfg.scratch.map { _ => Seq(
TLClientParameters(
name = s"Core xx DCache MMIO",
sourceId = IdRange(0, cfg.nMMIOs),
requestFifo = true))
} getOrElse { Seq(
TLClientParameters(
name = s"Core xx DCache MMIO",
sourceId = IdRange(0, firstMMIO),
supportsProbe = TransferSizes(1, cfg.blockBytes)),
TLClientParameters(
name = s"Core xx DCache",
sourceId = IdRange(firstMMIO, firstMMIO+cfg.nMMIOs),
requestFifo = true))
},

2
src/main/scala/rocket/ICache.scala
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@ -36,7 +36,7 @@ class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICache
class ICache(val latency: Int, val hartid: Int)(implicit p: Parameters) extends LazyModule
with HasRocketCoreParameters {
lazy val module = new ICacheModule(this)
val masterNode = TLClientNode(TLClientParameters(sourceId = IdRange(0,1)))
val masterNode = TLClientNode(TLClientParameters(name = s"Core ${hartid} ICache"))
val icacheParams = tileParams.icache.get
val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes