From d1c83ccda0c9a59add21598b9638ba63ac521344 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 13 Jun 2016 16:18:38 -0700 Subject: [PATCH] change Tile interface to allow arbitrary number of cached and uncached channels --- rocket/src/main/scala/tile.scala | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 14c51966..fca46187 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -9,6 +9,8 @@ import cde.{Parameters, Field} case object CoreName extends Field[String] case object BuildRoCC extends Field[Seq[RoccParameters]] +case object NCachedTileLinkPorts extends Field[Int] +case object NUncachedTileLinkPorts extends Field[Int] case class RoccParameters( opcodes: OpcodeSet, @@ -20,22 +22,23 @@ case class RoccParameters( abstract class Tile(resetSignal: Bool = null) (implicit p: Parameters) extends Module(_reset = resetSignal) { - val buildRocc = p(BuildRoCC) - val usingRocc = !buildRocc.isEmpty - val nRocc = buildRocc.size - val nFPUPorts = buildRocc.filter(_.useFPU).size - val nCachedTileLinkPorts = 1 - val nUncachedTileLinkPorts = 1 + p(RoccNMemChannels) + val nCachedTileLinkPorts = p(NCachedTileLinkPorts) + val nUncachedTileLinkPorts = p(NUncachedTileLinkPorts) val dcacheParams = p.alterPartial({ case CacheName => "L1D" }) + val io = new Bundle { val cached = Vec(nCachedTileLinkPorts, new ClientTileLinkIO) val uncached = Vec(nUncachedTileLinkPorts, new ClientUncachedTileLinkIO) val prci = new PRCITileIO().flip - val dma = new DmaIO } } class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(resetSignal)(p) { + val buildRocc = p(BuildRoCC) + val usingRocc = !buildRocc.isEmpty + val nRocc = buildRocc.size + val nFPUPorts = buildRocc.filter(_.useFPU).size + val core = Module(new Rocket()(p.alterPartial({ case CoreName => "Rocket" }))) val icache = Module(new Frontend()(p.alterPartial({ case CacheName => "L1I"