riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Periphery: make bus width and arithmetic atomics configurable (#337)

Browse Source
This commit is contained in:
Wesley W. Terpstra
2016-09-23 15:25:58 -07:00
committed by Yunsup Lee
parent 47843d8ec1
commit d175bb314d
4 changed files with 24 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/uncore/devices/Prci.scala
View File

@ -48,7 +48,7 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep
val timeWidth = 64
val regWidth = 32
// demand atomic accesses for RV64
require(c.beatBytes == (p(rocket.XLen) min timeWidth)/8)
require(c.beatBytes >= (p(rocket.XLen) min timeWidth)/8)
val time = Seq.fill(timeWidth/regWidth)(Reg(init=UInt(0, width = regWidth)))
when (io.rtcTick) {