riscv/rocket-chip
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Periphery: make bus width and arithmetic atomics configurable (#337)

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This commit is contained in:
Wesley W. Terpstra
2016-09-23 15:25:58 -07:00
committed by Yunsup Lee
parent 47843d8ec1
commit d175bb314d
4 changed files with 24 additions and 10 deletions
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7
src/main/scala/rocketchip/BaseTop.scala
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@@ -49,7 +49,12 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
val legacy = LazyModule(new TLLegacy()(p.alterPartial({ case TLId => "L2toMMIO" })))
peripheryBus.node := TLWidthWidget(legacy.tlDataBytes)(TLBuffer()(TLAtomicAutomata()(TLHintHandler()(legacy.node))))
peripheryBus.node :=
TLWidthWidget(legacy.tlDataBytes)(
TLBuffer()(
TLAtomicAutomata(arithmetic = p(PeripheryBusKey).arithAMO)(
TLHintHandler()(
legacy.node))))
}
abstract class BaseTopBundle(val p: Parameters) extends Bundle {