diff --git a/src/main/scala/regmapper/RegField.scala b/src/main/scala/regmapper/RegField.scala
index d676ec79..b814732b 100644
--- a/src/main/scala/regmapper/RegField.scala
+++ b/src/main/scala/regmapper/RegField.scala
@@ -26,7 +26,7 @@ case class RegFieldDesc (
   groupDesc: Option[String] = None,
   access: RegFieldAccessType = RegFieldAccessType.RW,
   reset: Option[BigInt] = None,
-  enumerations: Map[String, BigInt] = Map()
+  enumerations: Map[BigInt, (String, String)] = Map()
 ){
 }
 
diff --git a/src/main/scala/tilelink/RegisterRouter.scala b/src/main/scala/tilelink/RegisterRouter.scala
index 55b58fe4..6b14adc1 100644
--- a/src/main/scala/tilelink/RegisterRouter.scala
+++ b/src/main/scala/tilelink/RegisterRouter.scala
@@ -93,11 +93,17 @@ case class TLRegisterNode(
             ("bitOffset"   -> currentBitOffset) ~
             ("bitWidth"    -> f.width) ~
             ("name" -> f.desc.map(_.name)) ~
-            ("description" -> f.desc.map{ d=> if (d.desc == "") None else Some(d.desc)}) ~
+            ("description" -> f.desc.map{d => if (d.desc == "") None else Some(d.desc)}) ~
             ("resetValue"  -> f.desc.map{_.reset}) ~
             ("group"       -> f.desc.map{_.group}) ~
             ("groupDesc"   -> f.desc.map{_.groupDesc}) ~
-            ("accessType"  -> f.desc.map {d => d.access.toString})
+            ("accessType"  -> f.desc.map {d => d.access.toString}) ~
+            ("enumerations" -> f.desc.map {d =>
+              Option(d.enumerations.map { case (key, (name, desc)) =>
+                (("value" -> key) ~
+                  ("name" -> name) ~
+                  ("description" -> desc))
+              }).filter(_.nonEmpty)})
         ))
         currentBitOffset = currentBitOffset + f.width
         tmp