riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Merge pull request #804 from freechipsproject/travis_cache_stages

Browse Source 
travis: attempt to make 2 build stages for cache
This commit is contained in:
Megan Wachs 2017-06-16 07:31:56 -07:00 committed by GitHub
commit d0f8cdd00c
1 changed files with 7 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
.travis.yml
View File

@ -43,13 +43,18 @@ branches:
jobs: jobs:
include: include:
- stage: prepare cache - stage: prepare cache-riscv-tools
script: script:
- travis_wait 120 make tools verilator -C regression SUITE=none - travis_wait 120 make tools -C regression SUITE=none
before_install: before_install:
- export CXX=g++-4.8 CC=gcc-4.8 - export CXX=g++-4.8 CC=gcc-4.8
before_cache: before_cache:
- ls -t regression/install | tail -n+2 | sed s@^@regression/install/@ | xargs rm -rf - ls -t regression/install | tail -n+2 | sed s@^@regression/install/@ | xargs rm -rf
- stage: prepare cache-verilator
script:
- travis_wait 120 make verilator -C regression SUITE=none
before_install:
- export CXX=g++-4.8 CC=gcc-4.8
- &test - &test
stage: Test stage: Test
script: script: