From d0f3004097336bfff9222bf7e472308c159e7a12 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 24 Apr 2017 15:13:58 -0700 Subject: [PATCH] tilelink2: help tools save some registers in the WidthWidget (#691) --- src/main/scala/uncore/tilelink2/WidthWidget.scala | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/main/scala/uncore/tilelink2/WidthWidget.scala b/src/main/scala/uncore/tilelink2/WidthWidget.scala index 36e154b3..5c84b8b3 100644 --- a/src/main/scala/uncore/tilelink2/WidthWidget.scala +++ b/src/main/scala/uncore/tilelink2/WidthWidget.scala @@ -132,7 +132,13 @@ class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyMod } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) - repeat := split(edgeIn, Repeater(in, repeat), edgeOut, out) + val repeated = Repeater(in, repeat) + val cated = Wire(repeated) + cated <> repeated + edgeIn.data(cated.bits) := Cat( + edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8), + edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0)) + repeat := split(edgeIn, cated, edgeOut, out) } else { // merge input to output merge(edgeIn, in, edgeOut, out)