From d0e350976a367bab2513c5b5b938f2ae5dfac965 Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Date: Fri, 23 Feb 2018 15:32:10 -0500
Subject: [PATCH] Add jtag_vpi.c to sources for vsim

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
---
 vsim/Makefrag | 1 +
 1 file changed, 1 insertion(+)

diff --git a/vsim/Makefrag b/vsim/Makefrag
index db0e6d4c..8806f561 100644
--- a/vsim/Makefrag
+++ b/vsim/Makefrag
@@ -25,6 +25,7 @@ sim_csrcs = \
 	$(base_dir)/csrc/SimDTM.cc \
         $(base_dir)/csrc/SimJTAG.cc \
         $(base_dir)/csrc/remote_bitbang.cc \
+        $(base_dir)/csrc/jtag_vpi.c
 
 #--------------------------------------------------------------------
 # Build Verilog