diff --git a/vsim/Makefrag b/vsim/Makefrag
index db0e6d4c..8806f561 100644
--- a/vsim/Makefrag
+++ b/vsim/Makefrag
@@ -25,6 +25,7 @@ sim_csrcs = \
 	$(base_dir)/csrc/SimDTM.cc \
         $(base_dir)/csrc/SimJTAG.cc \
         $(base_dir)/csrc/remote_bitbang.cc \
+        $(base_dir)/csrc/jtag_vpi.c
 
 #--------------------------------------------------------------------
 # Build Verilog