Improve frontend branch prediction
- Put correctness responsibility on Frontend, not IBuf, for improved separation of concerns. Frontend must detect case that the BTB predicts a taken branch in the middle of an instruction. - Pass BTB information down pipeline unconditionally, fixing case that screws up the branch history when the BTB misses and the instruction is misaligned. - Remove jumpInFrontend option; it's now unconditional. - Default to one-bit counters in the BHT. For tiny BHTs like these, it's more resource efficient to have a larger index space than to have hysteresis.
This commit is contained in:
Andrew Waterman
@ -28,7 +28,7 @@ class FrontendExceptions extends Bundle {
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}
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class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) {
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val btb = Valid(new BTBResp)
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val btb = new BTBResp
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val pc = UInt(width = vaddrBitsExtended) // ID stage PC
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val data = UInt(width = fetchWidth * coreInstBits)
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val mask = Bits(width = fetchWidth)
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@ -86,6 +86,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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val s2_pc = RegInit(t = UInt(width = vaddrBitsExtended), alignPC(io.reset_vector))
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val s2_btb_resp_valid = if (usingBTB) Reg(Bool()) else false.B
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val s2_btb_resp_bits = Reg(new BTBResp)
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val s2_btb_taken = s2_btb_resp_valid && s2_btb_resp_bits.taken
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val s2_tlb_resp = Reg(tlb.io.resp)
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val s2_xcpt = s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst
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val s2_speculative = Reg(init=Bool(false))
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@ -143,13 +144,14 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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fq.io.enq.bits.data := icache.io.resp.bits.data
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fq.io.enq.bits.mask := UInt((1 << fetchWidth)-1) << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
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fq.io.enq.bits.replay := icache.io.resp.bits.replay || icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt
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fq.io.enq.bits.btb.valid := s2_btb_resp_valid
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fq.io.enq.bits.btb.bits := s2_btb_resp_bits
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fq.io.enq.bits.btb := s2_btb_resp_bits
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fq.io.enq.bits.btb.taken := s2_btb_taken
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fq.io.enq.bits.xcpt := s2_tlb_resp
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when (icache.io.resp.valid && icache.io.resp.bits.ae) { fq.io.enq.bits.xcpt.ae.inst := true }
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if (usingBTB) {
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val btb = Module(new BTB)
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btb.io.flush := false
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btb.io.req.valid := false
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btb.io.req.bits.addr := s1_pc
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btb.io.btb_update := io.cpu.btb_update
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@ -166,111 +168,123 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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predicted_taken := Bool(true)
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}
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if (!coreParams.jumpInFrontend) {
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// push RAS speculatively
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btb.io.ras_update.valid := btb.io.req.valid && btb.io.resp.valid && btb.io.resp.bits.cfiType.isOneOf(CFIType.call, CFIType.ret)
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val returnAddrLSBs = btb.io.resp.bits.bridx +& 1
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btb.io.ras_update.bits.returnAddr :=
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Mux(returnAddrLSBs(log2Ceil(fetchWidth)), ntpc, s1_base_pc | ((returnAddrLSBs << log2Ceil(coreInstBytes)) & (fetchBytes - 1)))
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btb.io.ras_update.bits.cfiType := btb.io.resp.bits.cfiType
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btb.io.ras_update.bits.prediction.valid := true
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} else {
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val s2_btb_hit = s2_btb_resp_valid && s2_btb_resp_bits.taken
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val s2_base_pc = ~(~s2_pc | (fetchBytes-1))
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val taken_idx = Wire(UInt())
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val after_idx = Wire(UInt())
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val useRAS = Wire(init=false.B)
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val s2_base_pc = ~(~s2_pc | (fetchBytes-1))
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val taken_idx = Wire(UInt())
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val after_idx = Wire(UInt())
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val useRAS = Wire(init=false.B)
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val updateBTB = Wire(init=false.B)
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def scanInsns(idx: Int, prevValid: Bool, prevBits: UInt, prevTaken: Bool): Bool = {
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val prevRVI = prevValid && prevBits(1,0) === 3
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val valid = fq.io.enq.bits.mask(idx) && !prevRVI
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val bits = fq.io.enq.bits.data(coreInstBits*(idx+1)-1, coreInstBits*idx)
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val rvc = bits(1,0) =/= 3
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val rviBits = Cat(bits, prevBits)
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val rviBranch = rviBits(6,0) === Instructions.BEQ.value.asUInt()(6,0)
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val rviJump = rviBits(6,0) === Instructions.JAL.value.asUInt()(6,0)
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val rviJALR = rviBits(6,0) === Instructions.JALR.value.asUInt()(6,0)
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val rviReturn = rviJALR && !rviBits(7) && BitPat("b00?01") === rviBits(19,15)
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val rviCall = (rviJALR || rviJump) && rviBits(7)
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val rvcBranch = bits === Instructions.C_BEQZ || bits === Instructions.C_BNEZ
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val rvcJAL = Bool(xLen == 32) && bits === Instructions.C_JAL
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val rvcJump = bits === Instructions.C_J || rvcJAL
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val rvcImm = Mux(bits(14), new RVCDecoder(bits).bImm.asSInt, new RVCDecoder(bits).jImm.asSInt)
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val rvcJR = bits === Instructions.C_MV && bits(6,2) === 0
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val rvcReturn = rvcJR && BitPat("b00?01") === bits(11,7)
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val rvcJALR = bits === Instructions.C_ADD && bits(6,2) === 0
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val rvcCall = rvcJAL || rvcJALR
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val rviImm = Mux(rviBits(3), ImmGen(IMM_UJ, rviBits), ImmGen(IMM_SB, rviBits))
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val taken =
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prevRVI && (rviJump || rviJALR || rviBranch && s2_btb_resp_bits.bht.taken) ||
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valid && (rvcJump || rvcJALR || rvcJR || rvcBranch && s2_btb_resp_bits.bht.taken)
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val predictReturn = btb.io.ras_head.valid && (prevRVI && rviReturn || valid && rvcReturn)
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val predictBranch =
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prevRVI && (rviJump || rviBranch && s2_btb_resp_bits.bht.taken) ||
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valid && (rvcJump || rvcBranch && s2_btb_resp_bits.bht.taken)
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def scanInsns(idx: Int, prevValid: Bool, prevBits: UInt, prevTaken: Bool): Bool = {
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def insnIsRVC(bits: UInt) = bits(1,0) =/= 3
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val prevRVI = prevValid && !insnIsRVC(prevBits)
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val valid = fq.io.enq.bits.mask(idx) && !prevRVI
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val bits = fq.io.enq.bits.data(coreInstBits*(idx+1)-1, coreInstBits*idx)
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val rvc = insnIsRVC(bits)
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val rviBits = Cat(bits, prevBits)
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val rviBranch = rviBits(6,0) === Instructions.BEQ.value.asUInt()(6,0)
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val rviJump = rviBits(6,0) === Instructions.JAL.value.asUInt()(6,0)
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val rviJALR = rviBits(6,0) === Instructions.JALR.value.asUInt()(6,0)
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val rviReturn = rviJALR && !rviBits(7) && BitPat("b00?01") === rviBits(19,15)
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val rviCall = (rviJALR || rviJump) && rviBits(7)
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val rvcBranch = bits === Instructions.C_BEQZ || bits === Instructions.C_BNEZ
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val rvcJAL = Bool(xLen == 32) && bits === Instructions.C_JAL
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val rvcJump = bits === Instructions.C_J || rvcJAL
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val rvcImm = Mux(bits(14), new RVCDecoder(bits).bImm.asSInt, new RVCDecoder(bits).jImm.asSInt)
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val rvcJR = bits === Instructions.C_MV && bits(6,2) === 0
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val rvcReturn = rvcJR && BitPat("b00?01") === bits(11,7)
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val rvcJALR = bits === Instructions.C_ADD && bits(6,2) === 0
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val rvcCall = rvcJAL || rvcJALR
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val rviImm = Mux(rviBits(3), ImmGen(IMM_UJ, rviBits), ImmGen(IMM_SB, rviBits))
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val taken =
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prevRVI && (rviJump || rviJALR || rviBranch && s2_btb_resp_bits.bht.taken) ||
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valid && (rvcJump || rvcJALR || rvcJR || rvcBranch && s2_btb_resp_bits.bht.taken)
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val predictReturn = btb.io.ras_head.valid && (prevRVI && rviReturn || valid && rvcReturn)
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val predictJump = prevRVI && rviJump || valid && rvcJump
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val predictBranch = s2_btb_resp_bits.bht.taken && (prevRVI && rviBranch || valid && rvcBranch)
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when (!prevTaken) {
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taken_idx := idx
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after_idx := idx + 1
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btb.io.ras_update.valid := fq.io.enq.fire() && !wrong_path && (prevRVI && (rviCall || rviReturn) || valid && (rvcCall || rvcReturn))
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btb.io.ras_update.bits.prediction.valid := true
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btb.io.ras_update.bits.cfiType := Mux(Mux(prevRVI, rviReturn, rvcReturn), CFIType.ret, CFIType.call)
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when (s2_valid && s2_btb_resp_valid && s2_btb_resp_bits.bridx === idx && valid && !rvc) {
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// The BTB has predicted that the middle of an RVI instruction is
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// a branch! Flush the BTB and the pipeline.
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btb.io.flush := true
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fq.io.enq.bits.replay := true
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}
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when (!s2_btb_hit) {
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when (fq.io.enq.fire() && taken && !predictBranch && !predictReturn) {
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wrong_path := true
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}
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when (s2_valid && predictReturn) {
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useRAS := true
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}
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when (s2_valid && predictBranch) {
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val pc = s2_base_pc | (idx*coreInstBytes)
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val npc =
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if (idx == 0) pc.asSInt + Mux(prevRVI, rviImm -& 2.S, rvcImm)
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else Mux(prevRVI, pc - coreInstBytes, pc).asSInt + Mux(prevRVI, rviImm, rvcImm)
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predicted_npc := npc.asUInt
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}
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when (!prevTaken) {
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taken_idx := idx
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after_idx := idx + 1
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btb.io.ras_update.valid := fq.io.enq.fire() && !wrong_path && (prevRVI && (rviCall || rviReturn) || valid && (rvcCall || rvcReturn))
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btb.io.ras_update.bits.cfiType := Mux(Mux(prevRVI, rviReturn, rvcReturn), CFIType.ret,
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Mux(Mux(prevRVI, rviCall, rvcCall), CFIType.call,
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Mux(Mux(prevRVI, rviBranch, rvcBranch), CFIType.branch,
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CFIType.jump)))
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when (prevRVI && rviBranch || valid && rvcBranch) {
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btb.io.bht_advance.valid := fq.io.enq.fire() && !wrong_path && !s2_btb_resp_valid
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btb.io.bht_advance.bits := s2_btb_resp_bits
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}
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when (!s2_btb_taken) {
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when (fq.io.enq.fire() && taken && !predictBranch && !predictJump && !predictReturn) {
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wrong_path := true
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}
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when (s2_valid && predictReturn) {
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useRAS := true
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}
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when (s2_valid && (predictBranch || predictJump)) {
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val pc = s2_base_pc | (idx*coreInstBytes)
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val npc =
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if (idx == 0) pc.asSInt + Mux(prevRVI, rviImm -& 2.S, rvcImm)
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else Mux(prevRVI, pc - coreInstBytes, pc).asSInt + Mux(prevRVI, rviImm, rvcImm)
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predicted_npc := npc.asUInt
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}
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}
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when (prevRVI && rviBranch || valid && rvcBranch) {
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btb.io.bht_advance.valid := fq.io.enq.fire() && !wrong_path
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btb.io.bht_advance.bits := s2_btb_resp_bits
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}
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when (!s2_btb_resp_valid && (predictBranch && s2_btb_resp_bits.bht.strongly_taken || predictJump || predictReturn)) {
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updateBTB := true
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}
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}
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if (idx == fetchWidth-1) {
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when (fq.io.enq.fire()) {
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s2_partial_insn_valid := false
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when (valid && !prevTaken && !rvc) {
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s2_partial_insn_valid := true
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s2_partial_insn := bits | 0x3
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}
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if (idx == fetchWidth-1) {
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when (fq.io.enq.fire()) {
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s2_partial_insn_valid := false
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when (valid && !prevTaken && !rvc) {
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s2_partial_insn_valid := true
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s2_partial_insn := bits | 0x3
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}
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prevTaken || taken
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} else {
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scanInsns(idx + 1, valid, bits, prevTaken || taken)
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}
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}
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btb.io.ras_update.bits.returnAddr := s2_base_pc + (after_idx << log2Ceil(coreInstBytes))
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val taken = scanInsns(0, s2_partial_insn_valid, s2_partial_insn, false.B)
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when (useRAS) {
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predicted_npc := btb.io.ras_head.bits
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}
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when (fq.io.enq.fire() && s2_btb_hit) {
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s2_partial_insn_valid := false
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}
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when (!s2_btb_hit) {
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fq.io.enq.bits.btb.bits.bridx := taken_idx
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when (taken) {
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fq.io.enq.bits.btb.valid := true
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fq.io.enq.bits.btb.bits.taken := true
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fq.io.enq.bits.btb.bits.entry := UInt(tileParams.btb.get.nEntries)
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when (fq.io.enq.fire()) { s2_redirect := true }
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}
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prevTaken || taken
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} else {
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scanInsns(idx + 1, valid, bits, prevTaken || taken)
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}
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}
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when (!io.cpu.btb_update.valid) {
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val fetch_bubble_likely = !fq.io.mask(1)
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btb.io.btb_update.valid := fq.io.enq.fire() && !wrong_path && fetch_bubble_likely && updateBTB
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btb.io.btb_update.bits.prediction.entry := UInt(tileParams.btb.get.nEntries)
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btb.io.btb_update.bits.isValid := true
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btb.io.btb_update.bits.cfiType := btb.io.ras_update.bits.cfiType
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btb.io.btb_update.bits.br_pc := s2_base_pc | (taken_idx << log2Ceil(coreInstBytes))
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btb.io.btb_update.bits.pc := s2_base_pc
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}
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btb.io.ras_update.bits.returnAddr := s2_base_pc + (after_idx << log2Ceil(coreInstBytes))
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val taken = scanInsns(0, s2_partial_insn_valid, s2_partial_insn, false.B)
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when (useRAS) {
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predicted_npc := btb.io.ras_head.bits
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}
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when (fq.io.enq.fire() && (s2_btb_taken || taken)) {
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s2_partial_insn_valid := false
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}
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when (!s2_btb_taken) {
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when (taken) {
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fq.io.enq.bits.btb.bridx := taken_idx
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fq.io.enq.bits.btb.taken := true
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fq.io.enq.bits.btb.entry := UInt(tileParams.btb.get.nEntries)
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when (fq.io.enq.fire()) { s2_redirect := true }
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}
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}
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assert(!s2_partial_insn_valid || fq.io.enq.bits.mask(0))
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when (s2_redirect) { s2_partial_insn_valid := false }
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when (io.cpu.req.valid) { wrong_path := false }
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}
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Block a user