Improve frontend branch prediction
- Put correctness responsibility on Frontend, not IBuf, for improved separation of concerns. Frontend must detect case that the BTB predicts a taken branch in the middle of an instruction. - Pass BTB information down pipeline unconditionally, fixing case that screws up the branch history when the BTB misses and the instruction is misaligned. - Remove jumpInFrontend option; it's now unconditional. - Default to one-bit counters in the BHT. For tiny BHTs like these, it's more resource efficient to have a larger index space than to have hysteresis.
This commit is contained in:
Andrew Waterman
@ -10,12 +10,18 @@ import freechips.rocketchip.coreplex.CacheBlockBytes
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import freechips.rocketchip.tile.HasCoreParameters
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import freechips.rocketchip.util._
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case class BHTParams(
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nEntries: Int = 512,
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counterLength: Int = 1,
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historyLength: Int = 8,
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historyBits: Int = 3)
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case class BTBParams(
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nEntries: Int = 28,
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nMatchBits: Int = 14,
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nPages: Int = 6,
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nRAS: Int = 6,
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nBHT: Int = 256,
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bhtParams: Option[BHTParams] = Some(BHTParams()),
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updatesOutOfOrder: Boolean = false)
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trait HasBtbParameters extends HasCoreParameters {
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@ -51,9 +57,10 @@ class RAS(nras: Int) {
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}
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class BHTResp(implicit p: Parameters) extends BtbBundle()(p) {
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val history = UInt(width = log2Up(btbParams.nBHT).max(1))
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val value = UInt(width = 2)
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val taken = Bool()
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val history = UInt(width = btbParams.bhtParams.map(_.historyLength).getOrElse(1))
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val value = UInt(width = btbParams.bhtParams.map(_.counterLength).getOrElse(1))
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def taken = value(0)
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def strongly_taken = value === 1
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}
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// BHT contains table of 2-bit counters and a global history register.
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@ -65,32 +72,43 @@ class BHTResp(implicit p: Parameters) extends BtbBundle()(p) {
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// - each counter corresponds with the address of the fetch packet ("fetch pc").
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// - updated when a branch resolves (and BTB was a hit for that branch).
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// The updating branch must provide its "fetch pc".
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class BHT(nbht: Int)(implicit val p: Parameters) extends HasCoreParameters {
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val nbhtbits = log2Up(nbht)
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class BHT(params: BHTParams)(implicit val p: Parameters) extends HasCoreParameters {
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def index(addr: UInt, history: UInt) = {
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def hashHistory(hist: UInt) = if (params.historyLength == params.historyBits) hist else {
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val k = math.sqrt(3)/2
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val i = BigDecimal(k * math.pow(2, params.historyLength)).toBigInt
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(i.U * hist)(params.historyLength-1, params.historyLength-params.historyBits)
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}
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def hashAddr(addr: UInt) = {
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val hi = addr >> log2Ceil(fetchBytes)
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hi(log2Ceil(params.nEntries)-1, 0) ^ (hi >> log2Ceil(params.nEntries))(1, 0)
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}
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hashAddr(addr) ^ (hashHistory(history) << (log2Up(params.nEntries) - params.historyBits))
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}
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def get(addr: UInt): BHTResp = {
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val res = Wire(new BHTResp)
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val index = addr(nbhtbits+log2Up(coreInstBytes)-1, log2Up(coreInstBytes)) ^ history
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res.value := table(index)
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res.value := table(index(addr, history))
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res.history := history
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res.taken := res.value(0)
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res
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}
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def updateTable(addr: UInt, d: BHTResp, taken: Bool): Unit = {
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val index = addr(nbhtbits+log2Up(coreInstBytes)-1, log2Up(coreInstBytes)) ^ d.history
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table(index) := Cat(taken, (d.value(1) & d.value(0)) | ((d.value(1) | d.value(0)) & taken))
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table(index(addr, d.history)) := (params.counterLength match {
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case 1 => taken
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case 2 => Cat(taken ^ d.value(0), d.value === 1 || d.value(1) && taken)
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})
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}
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def resetHistory(d: BHTResp): Unit = {
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history := d.history
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}
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def updateHistory(addr: UInt, d: BHTResp, taken: Bool): Unit = {
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history := Cat(taken, d.history(nbhtbits-1,1))
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history := Cat(taken, d.history >> 1)
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}
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def advanceHistory(taken: Bool): Unit = {
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history := Cat(taken, history(nbhtbits-1,1))
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history := Cat(taken, history >> 1)
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}
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private val table = Mem(nbht, UInt(width = 2))
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val history = Reg(UInt(width = nbhtbits))
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private val table = Mem(params.nEntries, UInt(width = params.counterLength))
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val history = Reg(UInt(width = params.historyLength))
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}
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object CFIType {
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@ -106,7 +124,7 @@ object CFIType {
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// - "pc" is what future fetch PCs will tag match against.
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// - "br_pc" is the PC of the branch instruction.
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class BTBUpdate(implicit p: Parameters) extends BtbBundle()(p) {
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val prediction = Valid(new BTBResp)
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val prediction = new BTBResp
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val pc = UInt(width = vaddrBits)
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val target = UInt(width = vaddrBits)
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val taken = Bool()
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@ -118,8 +136,9 @@ class BTBUpdate(implicit p: Parameters) extends BtbBundle()(p) {
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// BHT update occurs during branch resolution on all conditional branches.
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// - "pc" is what future fetch PCs will tag match against.
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class BHTUpdate(implicit p: Parameters) extends BtbBundle()(p) {
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val prediction = Valid(new BTBResp)
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val prediction = new BHTResp
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val pc = UInt(width = vaddrBits)
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val branch = Bool()
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val taken = Bool()
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val mispredict = Bool()
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}
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@ -127,7 +146,6 @@ class BHTUpdate(implicit p: Parameters) extends BtbBundle()(p) {
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class RASUpdate(implicit p: Parameters) extends BtbBundle()(p) {
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val cfiType = CFIType()
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val returnAddr = UInt(width = vaddrBits)
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val prediction = Valid(new BTBResp)
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}
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// - "bridx" is the low-order PC bits of the predicted branch (after
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@ -161,6 +179,7 @@ class BTB(implicit p: Parameters) extends BtbModule {
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val bht_advance = Valid(new BTBResp).flip
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val ras_update = Valid(new RASUpdate).flip
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val ras_head = Valid(UInt(width = vaddrBits))
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val flush = Bool().asInput
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}
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val idxs = Reg(Vec(entries, UInt(width=matchBits - log2Up(coreInstBytes))))
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@ -195,7 +214,7 @@ class BTB(implicit p: Parameters) extends BtbModule {
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if (updatesOutOfOrder) {
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val updateHits = (pageHit << 1)(Mux1H(idxMatch(r_btb_update.bits.pc), idxPages))
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(updateHits.orR, OHToUInt(updateHits))
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} else (r_btb_update.bits.prediction.valid && r_btb_update.bits.prediction.bits.entry < entries, r_btb_update.bits.prediction.bits.entry)
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} else (r_btb_update.bits.prediction.entry < entries, r_btb_update.bits.prediction.entry)
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val useUpdatePageHit = updatePageHit.orR
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val usePageHit = pageHit.orR
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@ -220,7 +239,7 @@ class BTB(implicit p: Parameters) extends BtbModule {
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val repl = new PseudoLRU(entries)
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val waddr = Mux(updateHit, updateHitAddr, repl.replace)
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val r_resp = Pipe(io.req.valid && io.resp.valid, io.resp.bits)
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val r_resp = Pipe(io.resp)
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when (r_resp.valid && r_resp.bits.taken || r_btb_update.valid) {
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repl.access(Mux(r_btb_update.valid, waddr, r_resp.bits.entry))
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}
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@ -262,24 +281,25 @@ class BTB(implicit p: Parameters) extends BtbModule {
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when (PopCountAtLeast(idxHit, 2)) {
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isValid := isValid & ~idxHit
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}
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when (io.flush) {
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isValid := 0
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}
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if (btbParams.nBHT > 0) {
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val bht = new BHT(btbParams.nBHT)
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if (btbParams.bhtParams.nonEmpty) {
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val bht = new BHT(btbParams.bhtParams.get)
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val isBranch = (idxHit & cfiType.map(_ === CFIType.branch).asUInt).orR
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val res = bht.get(io.req.bits.addr)
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when (io.req.valid && io.resp.valid && isBranch) {
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bht.advanceHistory(res.taken)
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}
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when (io.bht_advance.valid) {
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bht.advanceHistory(io.bht_advance.bits.bht.taken)
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}
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when (io.btb_update.valid) {
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bht.resetHistory(io.btb_update.bits.prediction.bits.bht)
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}
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when (io.bht_update.valid) {
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bht.updateTable(io.bht_update.bits.pc, io.bht_update.bits.prediction.bits.bht, io.bht_update.bits.taken)
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when (io.bht_update.bits.mispredict) {
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bht.updateHistory(io.bht_update.bits.pc, io.bht_update.bits.prediction.bits.bht, io.bht_update.bits.taken)
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when (io.bht_update.bits.branch) {
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bht.updateTable(io.bht_update.bits.pc, io.bht_update.bits.prediction, io.bht_update.bits.taken)
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when (io.bht_update.bits.mispredict) {
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bht.updateHistory(io.bht_update.bits.pc, io.bht_update.bits.prediction, io.bht_update.bits.taken)
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}
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}.elsewhen (io.bht_update.bits.mispredict) {
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bht.resetHistory(io.bht_update.bits.prediction)
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}
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}
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when (!res.taken && isBranch) { io.resp.bits.taken := false }
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@ -297,7 +317,7 @@ class BTB(implicit p: Parameters) extends BtbModule {
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when (io.ras_update.valid) {
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when (io.ras_update.bits.cfiType === CFIType.call) {
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ras.push(io.ras_update.bits.returnAddr)
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}.elsewhen (io.ras_update.bits.cfiType === CFIType.ret && io.ras_update.bits.prediction.valid) {
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}.elsewhen (io.ras_update.bits.cfiType === CFIType.ret) {
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ras.pop()
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}
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}
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