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Align RoCCIO with new cloneType (#1270)

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- Aligns RoCC with #1232.
- Fixes #1268.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
This commit is contained in:
Schuyler Eldridge 2018-03-06 20:53:51 -05:00 committed by Henry Cook
parent f1bd9c99aa
commit d0b46c5b8f
1 changed files with 2 additions and 4 deletions
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6
src/main/scala/tile/LazyRoCC.scala
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@ -52,8 +52,6 @@ class RoCCCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val busy = Bool(OUTPUT) val busy = Bool(OUTPUT)
val interrupt = Bool(OUTPUT) val interrupt = Bool(OUTPUT)
val exception = Bool(INPUT) val exception = Bool(INPUT)
override def cloneType = new RoCCCoreIO()(p).asInstanceOf[this.type]
} }
/** Base classes for Diplomatic TL2 RoCC units **/ /** Base classes for Diplomatic TL2 RoCC units **/
@ -64,7 +62,7 @@ abstract class LazyRoCC(implicit p: Parameters) extends LazyModule {
val tlNode: TLNode = TLIdentityNode() val tlNode: TLNode = TLIdentityNode()
} }
class RoCCIO(outer: LazyRoCC)(implicit p: Parameters) extends RoCCCoreIO()(p) { class RoCCIO(val outer: LazyRoCC)(implicit p: Parameters) extends RoCCCoreIO()(p) {
// Should be handled differently, eventually // Should be handled differently, eventually
val ptw = Vec(p(RoccNPTWPorts), new TLBPTWIO) val ptw = Vec(p(RoccNPTWPorts), new TLBPTWIO)
val fpu_req = Decoupled(new FPInput) val fpu_req = Decoupled(new FPInput)
@ -264,7 +262,7 @@ class CharacterCountExampleModule(outer: CharacterCountExample)(implicit p: Para
with HasL1CacheParameters { with HasL1CacheParameters {
val cacheParams = tileParams.icache.get val cacheParams = tileParams.icache.get
private val blockOffset = blockOffBits private val blockOffset = blockOffBits
private val beatOffset = log2Up(cacheDataBits/8) private val beatOffset = log2Up(cacheDataBits/8)
val needle = Reg(UInt(width = 8)) val needle = Reg(UInt(width = 8))