riscv/rocket-chip
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rocket: allow scratchpad address to be configurable (#570)

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This commit is contained in:
Henry Cook
2017-03-06 21:35:45 -08:00
committed by GitHub
parent 229fb2251d
commit d0ae087587
8 changed files with 80 additions and 41 deletions
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3
src/main/scala/tile/BaseTile.scala
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@ -18,7 +18,6 @@ trait TileParams {
val dcache: Option[DCacheParams]
val rocc: Seq[RoCCParams]
val btb: Option[BTBParams]
val dataScratchpadBytes: Int
}
trait HasTileParameters {
@ -31,7 +30,7 @@ trait HasTileParameters {
val usingRoCC = !tileParams.rocc.isEmpty
val usingBTB = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0
val usingPTW = usingVM
val usingDataScratchpad = tileParams.dcache.isDefined && tileParams.dataScratchpadBytes > 0
val usingDataScratchpad = tileParams.dcache.flatMap(_.scratch).isDefined
def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + tileParams.rocc.size
}

3
src/main/scala/tile/L1Cache.scala
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@ -17,13 +17,14 @@ trait L1CacheParams {
def nTLBEntries: Int
def splitMetadata: Boolean
def ecc: Option[Code]
def blockBytes: Int
}
trait HasL1CacheParameters {
implicit val p: Parameters
val cacheParams: L1CacheParams
def cacheBlockBytes = p(CacheBlockBytes)
def cacheBlockBytes = cacheParams.blockBytes
def lgCacheBlockBytes = log2Up(cacheBlockBytes)
def nSets = cacheParams.nSets
def blockOffBits = lgCacheBlockBytes