rocket: allow scratchpad address to be configurable (#570)

src/main/scala/rocket/DCache.scala

@@ -116,7 +116,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   val s1_victim_way = Wire(init = replacer.way)
   val (s1_hit_way, s1_hit_state, s1_victim_meta) =
     if (usingDataScratchpad) {
-      require(nWays == 1)
       metaWriteArb.io.out.ready := true
       metaReadArb.io.out.ready := !metaWriteArb.io.out.valid
       val inScratchpad = outer.scratch().map(_.contains(s1_paddr)).getOrElse(Bool(false))

src/main/scala/rocket/HellaCache.scala

@@ -24,12 +24,22 @@ case class DCacheParams(
     nMSHRs: Int = 1,
     nSDQ: Int = 17,
     nRPQ: Int = 16,
-    nMMIOs: Int = 1) extends L1CacheParams {
+    nMMIOs: Int = 1,
+    blockBytes: Int = 64,
+    scratch: Option[BigInt] = None) extends L1CacheParams {
+
+  def dataScratchpadBytes: Int = scratch.map(_ => nSets*blockBytes).getOrElse(0)
+
   def replacement = new RandomReplacement(nWays)
+
+  require((!scratch.isDefined || nWays == 1),
+    "Scratchpad only allowed in direct-mapped cache.")
+  require((!scratch.isDefined || nMSHRs == 0),
+    "Scratchpad only allowed in blocking cache.")
+  require(isPow2(nSets), s"nSets($nSets) must be pow2")
 }
 
-trait HasL1HellaCacheParameters extends HasL1CacheParameters
-    with HasCoreParameters {
+trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters {
   val cacheParams = tileParams.dcache.get
   val cfg = cacheParams
 
@@ -50,9 +60,8 @@ trait HasL1HellaCacheParameters extends HasL1CacheParameters
   def lrscCycles = 32 // ISA requires 16-insn LRSC sequences to succeed
   def nIOMSHRs = cacheParams.nMMIOs
   def maxUncachedInFlight = cacheParams.nMMIOs
-  def dataScratchpadSize = tileParams.dataScratchpadBytes
+  def dataScratchpadSize = cacheParams.dataScratchpadBytes
 
-  require(isPow2(nSets), s"nSets($nSets) must be pow2")
   require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)")
   // TODO should rowBits even be seperably specifiable?
   require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)") 
@@ -123,9 +132,13 @@ class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) {
 
 abstract class HellaCache(implicit p: Parameters) extends LazyModule {
   private val cfg = p(TileKey).dcache.get
-  val node = TLClientNode(TLClientParameters(
-    sourceId = IdRange(0, cfg.nMSHRs + cfg.nMMIOs),
-    supportsProbe = TransferSizes(1, p(CacheBlockBytes))))
+  val node = TLClientNode(cfg.scratch.map { _ =>
+      TLClientParameters(sourceId = IdRange(0, cfg.nMMIOs))
+    } getOrElse {
+      TLClientParameters(
+        sourceId = IdRange(0, cfg.nMSHRs+cfg.nMMIOs),
+        supportsProbe = TransferSizes(1, cfg.blockBytes))
+    })
   val module: HellaCacheModule
 }
 

src/main/scala/rocket/ICache.scala

@@ -19,7 +19,8 @@ case class ICacheParams(
     nTLBEntries: Int = 8,
     cacheIdBits: Int = 0,
     splitMetadata: Boolean = false,
-    ecc: Option[Code] = None) extends L1CacheParams {
+    ecc: Option[Code] = None,
+    blockBytes: Int = 64) extends L1CacheParams {
   def replacement = new RandomReplacement(nWays)
 }
 

src/main/scala/rocket/ScratchpadSlavePort.scala

@@ -13,12 +13,12 @@ import uncore.tilelink2._
 import uncore.util._
 import util._
 
-class ScratchpadSlavePort(sizeBytes: Int)(implicit p: Parameters) extends LazyModule
+class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends LazyModule
     with HasCoreParameters {
   val device = new MemoryDevice
   val node = TLManagerNode(Seq(TLManagerPortParameters(
     Seq(TLManagerParameters(
-      address            = List(AddressSet(0x80000000L, BigInt(sizeBytes-1))),
+      address            = List(address),
       resources          = device.reg,
       regionType         = RegionType.UNCACHED,
       executable         = true,
@@ -110,9 +110,9 @@ class ScratchpadSlavePort(sizeBytes: Int)(implicit p: Parameters) extends LazyMo
 trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
   val module: CanHaveScratchpadModule
 
-  val sizeBytes = tileParams.dataScratchpadBytes
+  val scratch = tileParams.dcache.flatMap(d => d.scratch.map(s =>
+    LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1)))))
   val slaveNode = TLInputNode()
-  val scratch   = if (sizeBytes > 0) Some(LazyModule(new ScratchpadSlavePort(sizeBytes))) else None
 
   scratch foreach { lm => lm.node := TLFragmenter(p(XLen)/8, p(CacheBlockBytes))(slaveNode) }
 
@@ -123,7 +123,7 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
     finalNode.get.address(0)
   }
 
-  nDCachePorts += (sizeBytes > 0).toInt
+  nDCachePorts += (scratch.isDefined).toInt
 }
 
 trait CanHaveScratchpadBundle extends HasHellaCacheBundle with HasICacheFrontendBundle {