riscv/rocket-chip
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rocket: allow scratchpad address to be configurable (#570)

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This commit is contained in:
Henry Cook
2017-03-06 21:35:45 -08:00
committed by GitHub
parent 229fb2251d
commit d0ae087587
8 changed files with 80 additions and 41 deletions
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42
src/main/scala/coreplex/Configs.scala
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@ -35,9 +35,17 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
class WithNBigCores(n: Int) extends Config((site, here, up) => {
case RocketTilesKey => {
val big = RocketTileParams(
core = RocketCoreParams(mulDiv = Some(MulDivParams(mulUnroll = 8, mulEarlyOut = true, divEarlyOut = true))),
dcache = Some(DCacheParams(rowBits = site(L1toL2Config).beatBytes*8, nMSHRs = 2)),
icache = Some(ICacheParams(rowBits = site(L1toL2Config).beatBytes*8)))
core = RocketCoreParams(mulDiv = Some(MulDivParams(
mulUnroll = 8,
mulEarlyOut = true,
divEarlyOut = true))),
dcache = Some(DCacheParams(
rowBits = site(L1toL2Config).beatBytes*8,
nMSHRs = 2,
blockBytes = site(CacheBlockBytes))),
icache = Some(ICacheParams(
rowBits = site(L1toL2Config).beatBytes*8,
blockBytes = site(CacheBlockBytes))))
List.fill(n)(big) ++ up(RocketTilesKey, site)
}
})
@ -47,8 +55,19 @@ class WithNSmallCores(n: Int) extends Config((site, here, up) => {
val small = RocketTileParams(
core = RocketCoreParams(useVM = false, fpu = None),
btb = None,
dcache = Some(DCacheParams(rowBits = site(L1toL2Config).beatBytes*8, nSets = 64, nWays = 1, nTLBEntries = 4, nMSHRs = 0)),
icache = Some(ICacheParams(rowBits = site(L1toL2Config).beatBytes*8, nSets = 64, nWays = 1, nTLBEntries = 4)))
dcache = Some(DCacheParams(
rowBits = site(L1toL2Config).beatBytes*8,
nSets = 64,
nWays = 1,
nTLBEntries = 4,
nMSHRs = 0,
blockBytes = site(CacheBlockBytes))),
icache = Some(ICacheParams(
rowBits = site(L1toL2Config).beatBytes*8,
nSets = 64,
nWays = 1,
nTLBEntries = 4,
blockBytes = site(CacheBlockBytes))))
List.fill(n)(small) ++ up(RocketTilesKey, site)
}
})
@ -89,19 +108,6 @@ class WithCacheBlockBytes(linesize: Int) extends Config((site, here, up) => {
case CacheBlockBytes => linesize
})
/** Warning: applies only to the most recently added tile.
* TODO: For now, there can only be a single scratchpad in the design
* because its address is hardcoded.
*/
class WithDataScratchpad(size: Int) extends Config((site, here, up) => {
case RocketTilesKey => {
val prev = up(RocketTilesKey, site)
prev.head.copy(
dcache = prev.head.dcache.map(_.copy(nSets = size / site(CacheBlockBytes))),
dataScratchpadBytes = size) +: prev.tail
}
})
class WithL2Cache extends Config(Parameters.empty) // TODO: re-add L2
class WithL2Capacity(size_kb: Int) extends Config(Parameters.empty) // TODO: re-add L2
class WithNL2Ways(n: Int) extends Config(Parameters.empty) // TODO: re-add L2