riscv/rocket-chip
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More WIP on new memory map

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This commit is contained in:
Andrew Waterman
2016-04-28 16:15:31 -07:00
parent 1f211b37df
commit d0aa4c722d
10 changed files with 55 additions and 125 deletions
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4
src/main/scala/TestConfigs.scala
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@ -155,7 +155,3 @@ class TraceGenConfig extends Config(new With2Cores ++ new WithL2Cache ++ new Wit
class FancyMemtestConfig extends Config(
new With2Cores ++ new With2MemoryChannels ++ new With4BanksPerMemChannel ++
new WithMemtest ++ new WithL2Cache ++ new GroundTestConfig)
class MemoryMuxMemtestConfig extends Config(
new With2MemoryChannels ++ new WithOneOrMaxChannels ++
new WithMemtest ++ new GroundTestConfig)