riscv/rocket-chip
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More WIP on new memory map

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Andrew Waterman committed 2016-04-28 16:15:31 -07:00
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commit d0aa4c722d
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+55 -125
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src/main/scala/TestConfigs.scala
-4
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@@ -155,7 +155,3 @@ class TraceGenConfig extends Config(new With2Cores ++ new WithL2Cache ++ new Wit
class FancyMemtestConfig extends Config(
new With2Cores ++ new With2MemoryChannels ++ new With4BanksPerMemChannel ++
new WithMemtest ++ new WithL2Cache ++ new GroundTestConfig)
class MemoryMuxMemtestConfig extends Config(
new With2MemoryChannels ++ new WithOneOrMaxChannels ++
new WithMemtest ++ new GroundTestConfig)