More WIP on new memory map
This commit is contained in:
Andrew Waterman
@ -17,10 +17,6 @@ case object NTiles extends Field[Int]
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case object NMemoryChannels extends Field[Int]
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/** Number of banks per memory channel */
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case object NBanksPerMemoryChannel extends Field[Int]
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/** Maximum number of banks per memory channel, when configurable */
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case object MaxBanksPerMemoryChannel extends Field[Int]
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/** Dynamic memory channel configurations */
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case object MemoryChannelMuxConfigs extends Field[List[Int]]
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/** Least significant bit of address used for bank partitioning */
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case object BankIdLSB extends Field[Int]
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/** Number of outstanding memory requests */
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@ -61,7 +57,6 @@ trait HasTopLevelParameters {
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lazy val scrAddrBits = log2Up(nSCR)
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lazy val scrDataBits = 64
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lazy val scrDataBytes = scrDataBits / 8
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lazy val memoryChannelMuxConfigs = p(MemoryChannelMuxConfigs)
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//require(lsb + log2Up(nBanks) < mifAddrBits)
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}
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@ -80,6 +75,7 @@ class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
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class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
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val mem = Vec(nMemChannels, new NastiIO)
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val mmio = new NastiIO
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}
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object TopUtils {
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@ -125,9 +121,11 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
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uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten
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io.host <> uncore.io.host
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io.mmio <> uncore.io.mmio
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io.mem.zip(uncore.io.mem).foreach { case (outer, inner) =>
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TopUtils.connectNasti(outer, inner)
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outer <> inner
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// Memory cache type should be normal non-cacheable bufferable
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// TODO why is this happening here? Would 0000 (device) be OK instead?
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outer.ar.bits.cache := UInt("b0011")
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outer.aw.bits.cache := UInt("b0011")
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}
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@ -165,23 +163,14 @@ class Uncore(implicit val p: Parameters) extends Module
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val addrMap = p(GlobalAddrMap)
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val addrHashMap = new AddrHashMap(addrMap)
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val memSize = addrHashMap("mem").size
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val scrFile = Module(new SCRFile("UNCORE_SCR", 0))
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scrFile.io.smi <> htif.io.scr
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scrFile.io.scr.attach(Wire(init = UInt(nTiles)), "N_CORES")
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scrFile.io.scr.attach(Wire(init = UInt(memSize >> 20)), "MMIO_BASE")
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scrFile.io.scr.attach(Wire(init = UInt(addrHashMap("io:int:configstring").start >> 20)), "MMIO_BASE")
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// scrFile.io.scr <> (... your SCR connections ...)
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buildMMIONetwork(p.alterPartial({case TLId => "MMIO_Outermost"}))
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// Configures the enabled memory channels. This can't be changed while the
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// chip is actively using memory, as it both drops Nasti messages and garbles
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// all of memory.
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val memory_channel_mux_select = scrFile.io.scr.attach(
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Reg(UInt(width = log2Up(memoryChannelMuxConfigs.size))),
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"MEMORY_CHANNEL_MUX_SELECT")
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outmemsys.io.memory_channel_mux_select := memory_channel_mux_select
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// Wire the htif to the memory port(s) and host interface
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io.mem <> outmemsys.io.mem
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if(p(UseHtifClockDiv)) {
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@ -191,31 +180,26 @@ class Uncore(implicit val p: Parameters) extends Module
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}
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def buildMMIONetwork(implicit p: Parameters) = {
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val (ioBase, ioAddrMap) = addrHashMap.subMap("io")
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val ioAddrHashMap = new AddrHashMap(ioAddrMap, ioBase)
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val mmioNarrower = Module(new TileLinkIONarrower("L2toMMIO", "MMIO_Outermost"))
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val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, addrMap.tail, memSize))
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val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap, ioBase))
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mmioNarrower.io.in <> outmemsys.io.mmio
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mmioNetwork.io.in.head <> mmioNarrower.io.out
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if (p(UseStreamLoopback)) {
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val lo_width = p(StreamLoopbackWidth)
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val lo_size = p(StreamLoopbackSize)
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val lo_conv = Module(new NastiIOStreamIOConverter(lo_width))
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val lo_port = addrHashMap("devices:loopback").port - 1
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TopUtils.connectTilelinkNasti(lo_conv.io.nasti, mmioNetwork.io.out(lo_port))
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lo_conv.io.stream.in <> Queue(lo_conv.io.stream.out, lo_size)
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}
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val rtc = Module(new RTC(p(NTiles)))
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val rtcAddr = addrHashMap("conf:rtc")
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val rtcPort = rtcAddr.port - 1
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require(rtc.size <= rtcAddr.size)
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rtc.io.tl <> mmioNetwork.io.out(rtcPort)
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val rtcAddr = ioAddrHashMap("int:rtc")
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require(rtc.size <= rtcAddr.region.size)
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rtc.io.tl <> mmioNetwork.io.out(rtcAddr.port)
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io.timerIRQs := rtc.io.irqs
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val deviceTree = Module(new ROMSlave(p(ConfigString).toSeq))
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val dtPort = addrHashMap("conf:devicetree").port - 1
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deviceTree.io <> mmioNetwork.io.out(dtPort)
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val deviceTreeAddr = ioAddrHashMap("int:configstring")
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deviceTree.io <> mmioNetwork.io.out(deviceTreeAddr.port)
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TopUtils.connectTilelinkNasti(io.mmio, mmioNetwork.io.out(ioAddrHashMap("ext").port))
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}
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}
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@ -229,7 +213,6 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
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val htif_uncached = (new ClientUncachedTileLinkIO).flip
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val incoherent = Vec(nTiles, Bool()).asInput
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val mem = Vec(nMemChannels, new NastiIO)
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val memory_channel_mux_select = UInt(INPUT, log2Up(memoryChannelMuxConfigs.size))
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val mmio = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => "L2toMMIO"}))
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}
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@ -272,34 +255,20 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
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// TODO: the code to print this stuff should live somewhere else
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println("Generated Address Map")
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for ((name, base, size, _, _) <- addrHashMap.sortedEntries) {
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println(f"\t$name%s $base%x - ${base + size - 1}%x")
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for ((name, base, region) <- addrHashMap.sortedEntries) {
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println(f"\t$name%s $base%x - ${base + region.size - 1}%x")
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}
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println("Generated Configuration String")
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println(new String(p(ConfigString)))
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val channelConfigs = p(MemoryChannelMuxConfigs)
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require(channelConfigs.sortWith(_ > _)(0) == nMemChannels,
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"More memory channels elaborated than can be enabled")
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val mem_ic =
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if (channelConfigs.size == 1) {
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val ic = Module(new TileLinkMemoryInterconnect(
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nBanksPerMemChannel, nMemChannels)(outermostTLParams))
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ic
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} else {
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val nBanks = nBanksPerMemChannel * nMemChannels
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val ic = Module(new TileLinkMemorySelector(
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nBanks, nMemChannels, channelConfigs)(outermostTLParams))
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ic.io.select := io.memory_channel_mux_select
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ic
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}
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val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, nMemChannels)(outermostTLParams))
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for ((bank, i) <- managerEndpoints.zipWithIndex) {
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for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
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val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
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val narrow = Module(new TileLinkIONarrower("L2toMC", "Outermost"))
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unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
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narrow.io.in <> unwrap.io.out
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mem_ic.io.in(i) <> narrow.io.out
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icPort <> narrow.io.out
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}
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for ((nasti, tl) <- io.mem zip mem_ic.io.out)
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