Refactored uncore conf
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Henry Cook
parent
1d7f1a8182
commit
d0805359a5
@ -1 +1 @@
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Subproject commit 97ac6a154ce22a7e848cf18b2ad314564f4c7c5d
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Subproject commit fbe177a2c549bf3ecdfeda74f8ceb81ef96232b8
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@ -85,22 +85,14 @@ class CrossbarToHubShim[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkC
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io.in.ready := io.out.ready
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}
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class ReferenceChipCrossbarNetwork(endpoints: Seq[Component])(implicit conf: LogicalNetworkConfiguration) extends LogicalNetwork[TileLink](endpoints)(conf) {
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class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgent])(implicit conf: LogicalNetworkConfiguration) extends LogicalNetwork[TileLink](endpoints)(conf) {
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type TileLinkType = TileLink
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val io = Vec(endpoints.map(_ match { case t:Tile => {(new TileLinkType).flip}; case h:CoherenceHub => {new TileLinkType}})){ new TileLinkType }
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val io = Vec(endpoints.map(_ match { case t:ClientCoherenceAgent => {(new TileLinkType).flip}; case h:MasterCoherenceAgent => {new TileLinkType}})){ new TileLinkType }
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//If we allow all physical networks to be identical, we can use
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<<<<<<< HEAD
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//reflection to automatically create enough networks for any given
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//bundle containing LogicalNetworkIOs
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val tl = new TileLinkType
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=======
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//reflection to automatically create enough for any given bundle containing LogicalNetworkIOs
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val tl = new TileLinkType
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//val dataTypesPassedThroughEachPhysicalNetwork = tl.getClass.getMethods.filter( x =>
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// classOf[LogicalNetworkIO[Data]].isAssignableFrom(x.getReturnType)).map(
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// _.invoke(tl).asInstanceOf[LogicalNetworkIO[Data]].m.erasure)
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>>>>>>> f19fdc1c7d15c6fc9a1fce7cd97619a124ae2c91
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val payloadBitsForEachPhysicalNetwork = tl.getClass.getMethods.filter( x =>
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classOf[LogicalNetworkIO[Data]].isAssignableFrom(x.getReturnType)).map(
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_.invoke(tl).asInstanceOf[LogicalNetworkIO[Data]].bits)
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@ -109,39 +101,29 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[Component])(implicit conf: Log
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//Use reflection to get the subset of each node's TileLink
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//corresponding to each direction of dataflow and connect each sub-bundle
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<<<<<<< HEAD
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//to the appropriate port of the physical crossbar network, inserting
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//shims to convert headers and process flits in the process.
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=======
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//to the appropriate port of the physical crossbar network, converting the
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//headers in the process.
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//TODO: Introduce SerDes and flit/phit partitoning here
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>>>>>>> f19fdc1c7d15c6fc9a1fce7cd97619a124ae2c91
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endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => {
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val tileProducedSubBundles = io.getClass.getMethods.zipWithIndex.filter( x =>
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val logNetIOSubBundles = io.getClass.getMethods.filter( x =>
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classOf[LogicalNetworkIO[Data]].isAssignableFrom(x.getReturnType)).zipWithIndex
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val tileProducedSubBundles = logNetIOSubBundles.filter( x =>
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classOf[TileIO[Data]].isAssignableFrom(x._1.getReturnType)).map{ case (m,i) =>
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(m.invoke(io).asInstanceOf[TileIO[Data]],i) }
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val hubProducedSubBundles = io.getClass.getMethods.zipWithIndex.filter( x =>
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val hubProducedSubBundles = logNetIOSubBundles.filter( x =>
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classOf[HubIO[Data]].isAssignableFrom(x._1.getReturnType)).map{ case (m,i) =>
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(m.invoke(io).asInstanceOf[HubIO[Data]],i) }
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end match {
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case x:Tile => {
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case x:ClientCoherenceAgent => {
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tileProducedSubBundles.foreach{ case (sl,i) =>
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physicalNetworks(i).io.in(id) <> TileToCrossbarShim(sl) }
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hubProducedSubBundles.foreach{ case (sl,i) =>
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sl <> CrossbarToHubShim(physicalNetworks(i).io.out(id)) }
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}
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case y:CoherenceHub => {
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case y:MasterCoherenceAgent => {
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hubProducedSubBundles.foreach{ case (sl,i) =>
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<<<<<<< HEAD
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physicalNetworks(i).io.in(id) <> HubToCrossbarShim(sl) }
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tileProducedSubBundles.foreach{ case (sl,i) =>
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sl <> CrossbarToTileShim(physicalNetworks(i).io.out(id)) }
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=======
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physicalNetworks(i).io.in(id) <> HubToCrossbarShim(sl)}
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tileProducedSubBundles.foreach{ case (sl,i) =>
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sl <> CrossbarToTileShim(physicalNetworks(i).io.out(id))}
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>>>>>>> f19fdc1c7d15c6fc9a1fce7cd97619a124ae2c91
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}
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}
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}}
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@ -206,41 +188,36 @@ class ReferenceChipBackend extends VerilogBackend
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transforms += ((c: Component) => addMemPin(c))
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}
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class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[Tile])(implicit conf: UncoreConfiguration) extends Component
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class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent])(implicit conf: CoherenceHubConfiguration) extends Component
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{
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implicit val lnconf = conf.ln
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val io = new Bundle {
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val tiles = Vec(conf.ntiles) { new ioTileLink() }.flip
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val htif = new ioTileLink().flip
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val tiles = Vec(conf.ln.nTiles) { new TileLink }.flip
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val htif = new TileLink().flip
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val mem_backup = new ioMemSerialized(htif_width)
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val mem_backup_en = Bool(INPUT)
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val mem = new ioMemPipe
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}
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require(tileEndpoints.length == conf.ntiles)
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import rocket.Constants._
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val hub = new CoherenceHubBroadcast()(conf.copy(ntiles = conf.ntiles+1))
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val lnWithHtifConf = conf.ln.copy(nEndpoints = conf.ln.nEndpoints+1,
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idBits = log2Up(conf.ln.nEndpoints+1)+1,
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nTiles = conf.ln.nTiles+1)
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val chWithHtifConf = conf.copy(ln = lnWithHtifConf)
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require(tileEndpoints.length == lnWithHtifConf.nTiles)
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val hub = new CoherenceHubBroadcast()(chWithHtifConf)
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val llc_tag_leaf = Mem(1024, seqRead = true) { Bits(width = 72) }
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val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) }
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val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf)
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val mem_serdes = new MemSerdes(htif_width)
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<<<<<<< HEAD
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implicit val logNetConf = new LogicalNetworkConfiguration(conf.ntiles+1, conf.tile_id_bits+1, 1, conf.ntiles)
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val testNet = new ReferenceChipCrossbarNetwork(List(hub)++tileEndpoints)
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=======
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val ic = ICacheConfig(128, 2, conf.co.asInstanceOf[CoherencePolicyWithUncached], ntlb = 8, nbtb = 16)
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val dc = DCacheConfig(128, 4, conf.co.asInstanceOf[CoherencePolicyWithUncached], ntlb = 8,
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nmshr = 2, nrpq = 16, nsdq = 17)
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val rc = RocketConfiguration(2, conf.co.asInstanceOf[CoherencePolicyWithUncached], ic, dc,
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fpu = true, vec = true)
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implicit val logNetConf = new LogicalNetworkConfiguration(3, 4, 1, 2)
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val testNet = new ReferenceChipCrossbarNetwork(List(hub,new Tile()(rc),new Tile()(rc)))
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>>>>>>> f19fdc1c7d15c6fc9a1fce7cd97619a124ae2c91
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val testNet = new ReferenceChipCrossbarNetwork(List(hub)++tileEndpoints)(lnWithHtifConf)
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for (i <- 0 until conf.ntiles) {
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for (i <- 0 until conf.ln.nTiles) {
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hub.io.tiles(i) <> io.tiles(i)
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}
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hub.io.tiles(conf.ntiles) <> io.htif
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hub.io.tiles(conf.ln.nTiles) <> io.htif
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llc.io.cpu.req_cmd <> Queue(hub.io.mem.req_cmd)
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llc.io.cpu.req_data <> Queue(hub.io.mem.req_data, REFILL_CYCLES)
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@ -269,22 +246,23 @@ class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[Tile])(implicit conf
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io.mem_backup <> mem_serdes.io.narrow
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}
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class Uncore(htif_width: Int, tileEndpoints: Seq[Tile])(implicit conf: UncoreConfiguration) extends Component
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class Uncore(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent])(implicit conf: CoherenceHubConfiguration) extends Component
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{
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implicit val lnconf = conf.ln
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val io = new Bundle {
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val debug = new ioDebug()
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val host = new ioHost(htif_width)
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val mem_backup = new ioMemSerialized(htif_width)
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val mem_backup_en = Bool(INPUT)
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val mem = new ioMemPipe
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val tiles = Vec(conf.ntiles) { new ioTileLink() }.flip
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val htif = Vec(conf.ntiles) { new ioHTIF(conf.ntiles) }.flip
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val tiles = Vec(conf.ln.nTiles) { new TileLink }.flip
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val htif = Vec(conf.ln.nTiles) { new ioHTIF(conf.ln.nTiles) }.flip
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}
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val htif = new rocketHTIF(htif_width)
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htif.io.cpu <> io.htif
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val outmemsys = new OuterMemorySystem(htif_width, tileEndpoints)
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val outmemsys = new OuterMemorySystem(htif_width, tileEndpoints++List(htif))
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outmemsys.io.tiles <> io.tiles
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outmemsys.io.htif <> htif.io.mem
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io.mem <> outmemsys.io.mem
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@ -349,7 +327,8 @@ class Top extends Component {
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else new MICoherence
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}
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implicit val uconf = UncoreConfiguration(NTILES, log2Up(NTILES)+1, co)
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implicit val lnConf = LogicalNetworkConfiguration(NTILES+1, log2Up(NTILES)+1, 1, NTILES)
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implicit val chConf = CoherenceHubConfiguration(co, lnConf)
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val io = new ioTop(HTIF_WIDTH)
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@ -363,7 +342,7 @@ class Top extends Component {
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val uncore = new Uncore(HTIF_WIDTH, tileList)
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var error_mode = Bool(false)
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for (i <- 0 until uconf.ntiles) {
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for (i <- 0 until NTILES) {
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val hl = uncore.io.htif(i)
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val tl = uncore.io.tiles(i)
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2
uncore
2
uncore
@ -1 +1 @@
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Subproject commit 2a1bf09c4839680b25a0a8a910750a519ad3f2a4
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Subproject commit f11638a6c8a6e7f59967d360e99daf49dc4a3151
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