Allow reset vector to be set dynamically

A chip's power-up sequence, or awake-from-sleep sequence, may wish to
set the reset PC based upon dynamic properties, e.g., the settings of
external pins.  Support this by passing the reset vector to the Coreplex.
ExampleTop simply hard-wires the reset vector, as was the case before.

Additionally, allow MTVEC to *not* be reset.  In most cases, including
riscv-tests, pk, and bbl, overriding MTVEC is one of the first things
that the boot sequence does.  So the reset value is superfluous.

src/main/scala/rocketchip/Periphery.scala

@@ -311,7 +311,9 @@ trait PeripheryBootROM extends LazyModule {
   implicit val p: Parameters
   val peripheryBus: TLXbar
 
-  val rom = LazyModule(new TLROM(0x1000, 0x1000, GenerateBootROM(p)) { override def name = "bootrom" })
+  val address = 0x1000
+  val size = 0x1000
+  val rom = LazyModule(new TLROM(address, size, GenerateBootROM(p, address)) { override def name = "bootrom" })
   rom.node := TLFragmenter(peripheryBus.node, 4, 256)
 }
 
@@ -365,3 +367,10 @@ trait PeripheryTestBusMasterModule {
   implicit val p: Parameters
   val outer: PeripheryTestBusMaster
 }
+
+/////
+
+trait HardwiredResetVector {
+  val coreplex: Coreplex
+  coreplex.io.resetVector := UInt(0x1000) // boot ROM
+}