riscv/rocket-chip
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Use new Mul/Div parameters vs UseFastMulDiv (#48)

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* Use new Mul/Div parameters vs UseFastMulDiv

* Rename MulDivUnroll to MulUnroll
This commit is contained in:
mwachs5 2016-07-15 15:41:20 -07:00 committed by Andrew Waterman
parent 7cf44f9b25
commit cff8de9814
1 changed files with 7 additions and 4 deletions
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11
rocket/src/main/scala/rocket.scala
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@ -22,7 +22,8 @@ case object UseAtomics extends Field[Boolean]
case object UsePerfCounters extends Field[Boolean] case object UsePerfCounters extends Field[Boolean]
case object FastLoadWord extends Field[Boolean] case object FastLoadWord extends Field[Boolean]
case object FastLoadByte extends Field[Boolean] case object FastLoadByte extends Field[Boolean]
case object FastMulDiv extends Field[Boolean] case object MulUnroll extends Field[Int]
case object DivEarlyOut extends Field[Boolean]
case object CoreInstBits extends Field[Int] case object CoreInstBits extends Field[Int]
case object CoreDataBits extends Field[Int] case object CoreDataBits extends Field[Int]
case object CoreDCacheReqTagBits extends Field[Int] case object CoreDCacheReqTagBits extends Field[Int]
@ -43,7 +44,8 @@ trait HasCoreParameters extends HasAddrMapParameters {
val usingAtomics = p(UseAtomics) val usingAtomics = p(UseAtomics)
val usingFDivSqrt = p(FDivSqrt) val usingFDivSqrt = p(FDivSqrt)
val usingRoCC = !p(BuildRoCC).isEmpty val usingRoCC = !p(BuildRoCC).isEmpty
val usingFastMulDiv = p(FastMulDiv) val mulUnroll = p(MulUnroll)
val divEarlyOut = p(DivEarlyOut)
val fastLoadWord = p(FastLoadWord) val fastLoadWord = p(FastLoadWord)
val fastLoadByte = p(FastLoadByte) val fastLoadByte = p(FastLoadByte)
@ -286,8 +288,9 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
// multiplier and divider // multiplier and divider
val div = Module(new MulDiv(width = xLen, val div = Module(new MulDiv(width = xLen,
unroll = if(usingFastMulDiv) 8 else 1, unroll = mulUnroll,
earlyOut = usingFastMulDiv)) earlyOut = divEarlyOut))
div.io.req.valid := ex_reg_valid && ex_ctrl.div div.io.req.valid := ex_reg_valid && ex_ctrl.div
div.io.req.bits.dw := ex_ctrl.alu_dw div.io.req.bits.dw := ex_ctrl.alu_dw
div.io.req.bits.fn := ex_ctrl.alu_fn div.io.req.bits.fn := ex_ctrl.alu_fn