riscv/rocket-chip
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Use longname for ElaborationArtefact emission

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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
This commit is contained in:
Schuyler Eldridge 2018-01-15 16:53:36 -05:00
parent e52d52ae99
commit cfd49f87c1
2 changed files with 5 additions and 5 deletions
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2
emulator/Makefrag-verilator
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@ -60,7 +60,7 @@ VERILATOR_FLAGS := --top-module $(MODEL) \
--output-split-cfuncs 20000 \
-Wno-STMTDLY --x-assign unique \
-I$(base_dir)/vsrc \
-O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -DTEST_HARNESS=V$(MODEL) -include $(base_dir)/csrc/verilator.h -include $(generated_dir)/$(CONFIG).plusArgs"
-O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -DTEST_HARNESS=V$(MODEL) -include $(base_dir)/csrc/verilator.h -include $(generated_dir)/$(PROJECT).$(CONFIG).plusArgs"
cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
headers = $(wildcard $(base_dir)/csrc/*.h)

2
src/main/scala/util/GeneratorUtils.scala
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@ -134,7 +134,7 @@ trait GeneratorApp extends App with HasGeneratorUtilities {
/** Output files created as a side-effect of elaboration */
def generateArtefacts {
ElaborationArtefacts.files.foreach { case (extension, contents) =>
writeOutputFile(td, s"${names.configs}.${extension}", contents ())
writeOutputFile(td, s"$longName.$extension", contents ())
}
}
}