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diplomacy: capture SourceInfo at point of := in Edge parameters

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This commit is contained in:
Wesley W. Terpstra 2017-09-22 22:23:58 -07:00
parent 16969eb1f6
commit cfb7f13408
11 changed files with 60 additions and 49 deletions
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4
src/main/scala/amba/ahb/Nodes.scala
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@ -9,8 +9,8 @@ import freechips.rocketchip.diplomacy._
object AHBImp extends NodeImp[AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBEdgeParameters, AHBBundle]
{
def edgeO(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters, p: Parameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu, p)
def edgeI(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters, p: Parameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu, p)
def edgeO(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters, p: Parameters, sourceInfo: SourceInfo): AHBEdgeParameters = AHBEdgeParameters(pd, pu, p, sourceInfo)
def edgeI(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters, p: Parameters, sourceInfo: SourceInfo): AHBEdgeParameters = AHBEdgeParameters(pd, pu, p, sourceInfo)
def bundleO(eo: AHBEdgeParameters): AHBBundle = AHBBundle(eo.bundle)
def bundleI(ei: AHBEdgeParameters): AHBBundle = AHBBundle(ei.bundle)

4
src/main/scala/amba/ahb/Parameters.scala
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@ -3,6 +3,7 @@
package freechips.rocketchip.amba.ahb
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import scala.math.max
@ -92,7 +93,8 @@ object AHBBundleParameters
case class AHBEdgeParameters(
master: AHBMasterPortParameters,
slave: AHBSlavePortParameters,
params: Parameters)
params: Parameters,
sourceInfo: SourceInfo)
{
val bundle = AHBBundleParameters(master, slave)
}

4
src/main/scala/amba/apb/Nodes.scala
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@ -9,8 +9,8 @@ import freechips.rocketchip.diplomacy._
object APBImp extends NodeImp[APBMasterPortParameters, APBSlavePortParameters, APBEdgeParameters, APBEdgeParameters, APBBundle]
{
def edgeO(pd: APBMasterPortParameters, pu: APBSlavePortParameters, p: Parameters): APBEdgeParameters = APBEdgeParameters(pd, pu, p)
def edgeI(pd: APBMasterPortParameters, pu: APBSlavePortParameters, p: Parameters): APBEdgeParameters = APBEdgeParameters(pd, pu, p)
def edgeO(pd: APBMasterPortParameters, pu: APBSlavePortParameters, p: Parameters, sourceInfo: SourceInfo): APBEdgeParameters = APBEdgeParameters(pd, pu, p, sourceInfo)
def edgeI(pd: APBMasterPortParameters, pu: APBSlavePortParameters, p: Parameters, sourceInfo: SourceInfo): APBEdgeParameters = APBEdgeParameters(pd, pu, p, sourceInfo)
def bundleO(eo: APBEdgeParameters): APBBundle = APBBundle(eo.bundle)
def bundleI(ei: APBEdgeParameters): APBBundle = APBBundle(ei.bundle)

4
src/main/scala/amba/apb/Parameters.scala
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@ -3,6 +3,7 @@
package freechips.rocketchip.amba.apb
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import scala.math.max
@ -79,7 +80,8 @@ object APBBundleParameters
case class APBEdgeParameters(
master: APBMasterPortParameters,
slave: APBSlavePortParameters,
params: Parameters)
params: Parameters,
sourceInfo: SourceInfo)
{
val bundle = APBBundleParameters(master, slave)
}

4
src/main/scala/amba/axi4/Nodes.scala
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@ -9,8 +9,8 @@ import freechips.rocketchip.diplomacy._
object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4EdgeParameters, AXI4Bundle]
{
def edgeO(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters, p: Parameters): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu, p)
def edgeI(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters, p: Parameters): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu, p)
def edgeO(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters, p: Parameters, sourceInfo: SourceInfo): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu, p, sourceInfo)
def edgeI(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters, p: Parameters, sourceInfo: SourceInfo): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu, p, sourceInfo)
def bundleO(eo: AXI4EdgeParameters): AXI4Bundle = AXI4Bundle(eo.bundle)
def bundleI(ei: AXI4EdgeParameters): AXI4Bundle = AXI4Bundle(ei.bundle)

4
src/main/scala/amba/axi4/Parameters.scala
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@ -3,6 +3,7 @@
package freechips.rocketchip.amba.axi4
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import scala.math.max
@ -125,7 +126,8 @@ object AXI4BundleParameters
case class AXI4EdgeParameters(
master: AXI4MasterPortParameters,
slave: AXI4SlavePortParameters,
params: Parameters)
params: Parameters,
sourceInfo: SourceInfo)
{
val bundle = AXI4BundleParameters(master, slave)
}

44
src/main/scala/diplomacy/Nodes.scala
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@ -34,7 +34,7 @@ private case object MonitorsEnabled extends Field[Boolean](true)
// BI = Bundle type used when connecting to the inner side of the node
trait InwardNodeImp[DI, UI, EI, BI <: Data]
{
def edgeI(pd: DI, pu: UI, p: Parameters): EI
def edgeI(pd: DI, pu: UI, p: Parameters, sourceInfo: SourceInfo): EI
def bundleI(ei: EI): BI
def colour: String
def reverse: Boolean = false
@ -55,7 +55,7 @@ trait InwardNodeImp[DI, UI, EI, BI <: Data]
// BO = Bundle type used when connecting to the outer side of the node
trait OutwardNodeImp[DO, UO, EO, BO <: Data]
{
def edgeO(pd: DO, pu: UO, p: Parameters): EO
def edgeO(pd: DO, pu: UO, p: Parameters, sourceInfo: SourceInfo): EO
def bundleO(eo: EO): BO
// optional methods to track node graph
@ -127,7 +127,7 @@ trait InwardNode[DI, UI, BI <: Data] extends BaseNode with InwardNodeHandle[DI,
require (!numPI.isEmpty, s"No number of inputs would be acceptable to ${name}${lazyModule.line}")
require (numPI.start >= 0, s"${name} accepts a negative number of inputs${lazyModule.line}")
private val accPI = ListBuffer[(Int, OutwardNode[DI, UI, BI], NodeBinding, Parameters)]()
private val accPI = ListBuffer[(Int, OutwardNode[DI, UI, BI], NodeBinding, Parameters, SourceInfo)]()
private var iRealized = false
protected[diplomacy] def iPushed = accPI.size
@ -136,7 +136,7 @@ trait InwardNode[DI, UI, BI <: Data] extends BaseNode with InwardNodeHandle[DI,
val noIs = numPI.size == 1 && numPI.contains(0)
require (!noIs, s"${name}${lazyModule.line} was incorrectly connected as a sink" + info)
require (!iRealized, s"${name}${lazyModule.line} was incorrectly connected as a sink after its .module was used" + info)
accPI += ((index, node, binding, p))
accPI += ((index, node, binding, p, sourceInfo))
}
protected[diplomacy] lazy val iBindings = { iRealized = true; accPI.result() }
@ -159,7 +159,7 @@ trait OutwardNode[DO, UO, BO <: Data] extends BaseNode with OutwardNodeHandle[DO
require (!numPO.isEmpty, s"No number of outputs would be acceptable to ${name}${lazyModule.line}")
require (numPO.start >= 0, s"${name} accepts a negative number of outputs${lazyModule.line}")
private val accPO = ListBuffer[(Int, InwardNode [DO, UO, BO], NodeBinding, Parameters)]()
private val accPO = ListBuffer[(Int, InwardNode [DO, UO, BO], NodeBinding, Parameters, SourceInfo)]()
private var oRealized = false
protected[diplomacy] def oPushed = accPO.size
@ -168,7 +168,7 @@ trait OutwardNode[DO, UO, BO <: Data] extends BaseNode with OutwardNodeHandle[DO
val noOs = numPO.size == 1 && numPO.contains(0)
require (!noOs, s"${name}${lazyModule.line} was incorrectly connected as a source" + info)
require (!oRealized, s"${name}${lazyModule.line} was incorrectly connected as a source after its .module was used" + info)
accPO += ((index, node, binding, p))
accPO += ((index, node, binding, p, sourceInfo))
}
protected[diplomacy] lazy val oBindings = { oRealized = true; accPO.result() }
@ -192,22 +192,22 @@ sealed abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
protected[diplomacy] lazy val (oPortMapping, iPortMapping, oStar, iStar) = {
val oStars = oBindings.filter { case (_,_,b,_) => b == BIND_STAR }.size
val iStars = iBindings.filter { case (_,_,b,_) => b == BIND_STAR }.size
val oKnown = oBindings.map { case (_, n, b, _) => b match {
val oStars = oBindings.filter { case (_,_,b,_,_) => b == BIND_STAR }.size
val iStars = iBindings.filter { case (_,_,b,_,_) => b == BIND_STAR }.size
val oKnown = oBindings.map { case (_, n, b, _, _) => b match {
case BIND_ONCE => 1
case BIND_QUERY => n.iStar
case BIND_STAR => 0 }}.foldLeft(0)(_+_)
val iKnown = iBindings.map { case (_, n, b, _) => b match {
val iKnown = iBindings.map { case (_, n, b, _, _) => b match {
case BIND_ONCE => 1
case BIND_QUERY => n.oStar
case BIND_STAR => 0 }}.foldLeft(0)(_+_)
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
val oSum = oBindings.map { case (_, n, b, _) => b match {
val oSum = oBindings.map { case (_, n, b, _, _) => b match {
case BIND_ONCE => 1
case BIND_QUERY => n.iStar
case BIND_STAR => oStar }}.scanLeft(0)(_+_)
val iSum = iBindings.map { case (_, n, b, _) => b match {
val iSum = iBindings.map { case (_, n, b, _, _) => b match {
case BIND_ONCE => 1
case BIND_QUERY => n.oStar
case BIND_STAR => iStar }}.scanLeft(0)(_+_)
@ -218,22 +218,22 @@ sealed abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
(oSum.init zip oSum.tail, iSum.init zip iSum.tail, oStar, iStar)
}
lazy val oPorts = oBindings.flatMap { case (i, n, _, p) =>
lazy val oPorts = oBindings.flatMap { case (i, n, _, p, s) =>
val (start, end) = n.iPortMapping(i)
(start until end) map { j => (j, n, p) }
(start until end) map { j => (j, n, p, s) }
}
lazy val iPorts = iBindings.flatMap { case (i, n, _, p) =>
lazy val iPorts = iBindings.flatMap { case (i, n, _, p, s) =>
val (start, end) = n.oPortMapping(i)
(start until end) map { j => (j, n, p) }
(start until end) map { j => (j, n, p, s) }
}
protected[diplomacy] lazy val oParams: Seq[DO] = {
val o = mapParamsD(oPorts.size, iPorts.map { case (i, n, _) => n.oParams(i) })
val o = mapParamsD(oPorts.size, iPorts.map { case (i, n, _, _) => n.oParams(i) })
require (o.size == oPorts.size, s"Bug in diplomacy; ${name} has ${o.size} != ${oPorts.size} down/up outer parameters${lazyModule.line}")
o.map(outer.mixO(_, this))
}
protected[diplomacy] lazy val iParams: Seq[UI] = {
val i = mapParamsU(iPorts.size, oPorts.map { case (o, n, _) => n.iParams(o) })
val i = mapParamsU(iPorts.size, oPorts.map { case (o, n, _, _) => n.iParams(o) })
require (i.size == iPorts.size, s"Bug in diplomacy; ${name} has ${i.size} != ${iPorts.size} up/down inner parameters${lazyModule.line}")
i.map(inner.mixI(_, this))
}
@ -241,8 +241,8 @@ sealed abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
protected[diplomacy] def gco = if (iParams.size != 1) None else inner.getO(iParams(0))
protected[diplomacy] def gci = if (oParams.size != 1) None else outer.getI(oParams(0))
protected[diplomacy] lazy val edgesOut = (oPorts zip oParams).map { case ((i, n, p), o) => outer.edgeO(o, n.iParams(i), p) }
protected[diplomacy] lazy val edgesIn = (iPorts zip iParams).map { case ((o, n, p), i) => inner.edgeI(n.oParams(o), i, p) }
protected[diplomacy] lazy val edgesOut = (oPorts zip oParams).map { case ((i, n, p, s), o) => outer.edgeO(o, n.iParams(i), p, s) }
protected[diplomacy] lazy val edgesIn = (iPorts zip iParams).map { case ((o, n, p, s), i) => inner.edgeI(n.oParams(o), i, p, s) }
// If you need access to the edges of a foreign Node, use this method (in/out create bundles)
lazy val edges = Edges(edgesIn, edgesOut)
@ -250,7 +250,7 @@ sealed abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map(e => Wire(outer.bundleO(e)))
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn .map(e => Wire(inner.bundleI(e)))
protected[diplomacy] def danglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _), i) =>
protected[diplomacy] def danglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
@ -258,7 +258,7 @@ sealed abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
name = valName.name + "_out",
data = bundleOut(i))
}
protected[diplomacy] def danglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _), i) =>
protected[diplomacy] def danglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),

15
src/main/scala/tilelink/Edges.scala
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@ -11,8 +11,9 @@ import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters)
extends TLEdgeParameters(client, manager, params)
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) Bool(true) else {
@ -265,8 +266,9 @@ class TLEdge(
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters)
extends TLEdge(client, manager, params)
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def Acquire(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
@ -480,8 +482,9 @@ class TLEdgeOut(
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters)
extends TLEdge(client, manager, params)
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {

6
src/main/scala/tilelink/IntNodes.scala
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@ -61,12 +61,12 @@ object IntSinkPortSimple
Seq.fill(ports)(IntSinkPortParameters(Seq.fill(sinks)(IntSinkParameters())))
}
case class IntEdge(source: IntSourcePortParameters, sink: IntSinkPortParameters, params: Parameters)
case class IntEdge(source: IntSourcePortParameters, sink: IntSinkPortParameters, params: Parameters, sourceInfo: SourceInfo)
object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, IntEdge, IntEdge, Vec[Bool]]
{
def edgeO(pd: IntSourcePortParameters, pu: IntSinkPortParameters, p: Parameters): IntEdge = IntEdge(pd, pu, p)
def edgeI(pd: IntSourcePortParameters, pu: IntSinkPortParameters, p: Parameters): IntEdge = IntEdge(pd, pu, p)
def edgeO(pd: IntSourcePortParameters, pu: IntSinkPortParameters, p: Parameters, sourceInfo: SourceInfo): IntEdge = IntEdge(pd, pu, p, sourceInfo)
def edgeI(pd: IntSourcePortParameters, pu: IntSinkPortParameters, p: Parameters, sourceInfo: SourceInfo): IntEdge = IntEdge(pd, pu, p, sourceInfo)
def bundleO(eo: IntEdge): Vec[Bool] = Vec(eo.source.num, Bool())
def bundleI(ei: IntEdge): Vec[Bool] = Vec(ei.source.num, Bool())

12
src/main/scala/tilelink/Nodes.scala
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@ -14,8 +14,8 @@ case object TLCombinationalCheck extends Field[Boolean](false)
object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters, p: Parameters): TLEdgeOut = new TLEdgeOut(pd, pu, p)
def edgeI(pd: TLClientPortParameters, pu: TLManagerPortParameters, p: Parameters): TLEdgeIn = new TLEdgeIn(pd, pu, p)
def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters, p: Parameters, sourceInfo: SourceInfo): TLEdgeOut = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLClientPortParameters, pu: TLManagerPortParameters, p: Parameters, sourceInfo: SourceInfo): TLEdgeIn = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut): TLBundle = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn): TLBundle = TLBundle(ei.bundle)
@ -93,8 +93,8 @@ abstract class TLCustomNode(
object TLAsyncImp extends NodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edgeO(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu, p)
def edgeI(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu, p)
def edgeO(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def edgeI(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundleO(eo: TLAsyncEdgeParameters): TLAsyncBundle = new TLAsyncBundle(eo.bundle)
def bundleI(ei: TLAsyncEdgeParameters): TLAsyncBundle = new TLAsyncBundle(ei.bundle)
@ -132,8 +132,8 @@ case class TLAsyncSinkNode(depth: Int, sync: Int)(implicit valName: ValName)
object TLRationalImp extends NodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edgeO(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu, p)
def edgeI(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu, p)
def edgeO(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def edgeI(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundleO(eo: TLRationalEdgeParameters): TLRationalBundle = new TLRationalBundle(eo.bundle)
def bundleI(ei: TLRationalEdgeParameters): TLRationalBundle = new TLRationalBundle(ei.bundle)

8
src/main/scala/tilelink/Parameters.scala
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@ -3,6 +3,7 @@
package freechips.rocketchip.tilelink
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util.RationalDirection
@ -314,7 +315,8 @@ object TLBundleParameters
case class TLEdgeParameters(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters)
params: Parameters,
sourceInfo: SourceInfo)
{
val maxTransfer = max(client.maxTransfer, manager.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
@ -342,7 +344,7 @@ object TLAsyncBundleParameters
def union(x: Seq[TLAsyncBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
}
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo)
{
val bundle = TLAsyncBundleParameters(manager.depth, TLBundleParameters(client.base, manager.base))
}
@ -350,7 +352,7 @@ case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: T
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLManagerPortParameters)
case class TLRationalClientPortParameters(base: TLClientPortParameters)
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters)
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo)
{
val bundle = TLBundleParameters(client.base, manager.base)
}