riscv/rocket-chip
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writebacks on release network pass asm tests and bmarks

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Henry Cook 2013-02-28 18:25:47 -08:00
parent a0dc8d52d6
commit cf76665d09
1 changed files with 1 additions and 1 deletions
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src/main/scala/RocketChip.scala
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@ -331,7 +331,7 @@ class TopIO(htif_width: Int) extends Bundle {
} }
object DummyTopLevelConstants extends _root_.uncore.constants.CoherenceConfigConstants { object DummyTopLevelConstants extends _root_.uncore.constants.CoherenceConfigConstants {
val NTILES = 1 val NTILES = 2
val HTIF_WIDTH = 16 val HTIF_WIDTH = 16
val ENABLE_SHARING = true val ENABLE_SHARING = true
val ENABLE_CLEAN_EXCLUSIVE = true val ENABLE_CLEAN_EXCLUSIVE = true