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Merge pull request #878 from freechipsproject/fix-fifofixer

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tileink: FIFOFixer should cope with zero-latency devices
This commit is contained in:
Yunsup Lee
2017-07-19 20:22:16 -07:00
committed by GitHub
parent 4d784ad693 21954c1c73
commit cf75c2049d
1 changed files with 1 additions and 1 deletions
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src/main/scala/tilelink/FIFOFixer.scala
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@@ -74,8 +74,8 @@ class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Para
// Keep one bit for each source recording if there is an outstanding request that must be made FIFO // Keep one bit for each source recording if there is an outstanding request that must be made FIFO
// Sources unused in the stall signal calculation should be pruned by DCE // Sources unused in the stall signal calculation should be pruned by DCE
val flight = RegInit(Vec.fill(edgeIn.client.endSourceId) { Bool(false) }) val flight = RegInit(Vec.fill(edgeIn.client.endSourceId) { Bool(false) })
when (d_first && in.d.fire()) { flight(in.d.bits.source) := Bool(false) }
when (a_first && in.a.fire()) { flight(in.a.bits.source) := !a_notFIFO } when (a_first && in.a.fire()) { flight(in.a.bits.source) := !a_notFIFO }
when (d_first && in.d.fire()) { flight(in.d.bits.source) := Bool(false) }
val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c => val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c =>
val a_sel = c.sourceId.contains(in.a.bits.source) val a_sel = c.sourceId.contains(in.a.bits.source)