Support SFENCE.VMA rs1 argument

This one's a little invasive.  To flush a specific entry from the TLB, you
need to reuse its CAM port.  Since the TLB lookup can be on the critical
path, we wish to avoid muxing in another address.

This is simple on the data side, where the datapath already carries rs1 to
the TLB (it's the same path as the AMO address calculation).  It's trickier
for the I$, where the TLB lookup address comes from the fetch stage PC.
The trick is to temporarily redirect the PC to rs1, then redirect the PC
again to the instruction after SFENCE.VMA.

src/main/scala/uncore/Consts.scala

@@ -29,6 +29,7 @@ trait MemoryOpConstants {
   def M_FLUSH   = UInt("b10000") // write back dirty data and cede R/W permissions
   def M_PRODUCE = UInt("b10001") // write back dirty data and cede W permissions
   def M_CLEAN   = UInt("b10011") // write back dirty data and retain R/W permissions
+  def M_SFENCE  = UInt("b10100") // flush TLB
 
   def isAMO(cmd: UInt) = cmd(3) || cmd === M_XA_SWAP
   def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW