upgrade to new rocket; improve vlsi makefiles

chisel

@@ -1 +1 @@
-Subproject commit ef08a0e9ac8925c6acc7920286c9a1b60428e35c
+Subproject commit baad813c8da86cbc92d8f7ae12039652d152dd32

csrc/emulator.cc

@@ -23,21 +23,7 @@ int main(int argc, char** argv)
   const char* loadmem = NULL;
   FILE *vcdfile = NULL, *logfile = stderr;
   const char* failure = NULL;
-
-  // for disassembly
   disassembler disasm;
-  char if_inst_str[1024];
-  char id_inst_str[1024];
-  char ex_inst_str[1024];
-  char mem_inst_str[1024];
-  char wb_inst_str[1024];
-
-  // used to register values from EX stage for trace
-  uint64_t mem_reg_raddr1 = 0, mem_reg_raddr2 = 0;
-  uint64_t wb_reg_raddr1 = 0, wb_reg_raddr2 = 0;
-  uint64_t mem_reg_rs1 = 0, mem_reg_rs2 = 0, mem_reg_inst = 0, ex_reg_inst = 0;
-  uint64_t wb_reg_rs1 = 0, wb_reg_rs2 = 0, wb_reg_inst = 0;
-  uint64_t id_icache_miss = 0, if_icache_req = 0, id_itlb_miss = 0;
 
   for (int i = 1; i < argc; i++)
   {
@@ -68,17 +54,15 @@ int main(int argc, char** argv)
   demand(fcntl(fromhost_fd,F_GETFD) >= 0, "fromhost file not open");
   demand(fcntl(tohost_fd,F_GETFD) >= 0, "tohost file not open");
 
+  const size_t disasm_len = 24;
   if (vcd)
   {
     // Create a VCD file
     vcdfile = strcmp(vcd, "-") == 0 ? stdout : fopen(vcd, "w");
     assert(vcdfile);
     fprintf(vcdfile, "$scope module Testbench $end\n");
-    fprintf(vcdfile, "$var reg 256 NDISASM_IF if_instruction $end\n");
+    fprintf(vcdfile, "$var reg %d NDISASM_WB wb_instruction $end\n", disasm_len*8);
-    fprintf(vcdfile, "$var reg 256 NDISASM_ID id_instruction $end\n");
+    fprintf(vcdfile, "$var reg 64 NCYCLE cycle $end\n");
-    fprintf(vcdfile, "$var reg 256 NDISASM_EX ex_instruction $end\n");
-    fprintf(vcdfile, "$var reg 256 NDISASM_MEM mem_instruction $end\n");
-    fprintf(vcdfile, "$var reg 16 NCYCLE cycle $end\n");
     fprintf(vcdfile, "$upscope $end\n");
   }
 
@@ -148,59 +132,40 @@ int main(int argc, char** argv)
       break;
     }
 
-    if (log || (quiet && trace_count % 10000 == 0))
+    if (log || vcd)
     {
-      insn_t insn;
+      val_t wb_reg_inst = tile.Top_Tile_core_dpath__wb_reg_inst.lo_word();
-      insn.bits = wb_reg_inst;
+      val_t wb_waddr = wb_reg_inst >> 27;
-      strcpy(wb_inst_str, disasm.disassemble(insn).c_str());
+      val_t wb_reg_raddr1 = (wb_reg_inst >> 22) & 0x1f;
+      val_t wb_reg_raddr2 = (wb_reg_inst >> 17) & 0x1f;
+      val_t wb_reg_rs1 =  tile.Top_Tile_core_dpath__wb_reg_rs1.lo_word();
+      val_t wb_reg_rs2 =  tile.Top_Tile_core_dpath__wb_reg_rs2.lo_word();
 
-      fprintf(logfile, "C: %10lld [%ld] pc=[%011lx] W[r%2ld=%016lx][%ld] R[r%2ld=%016lx] R[r%2ld=%016lx] inst=[%08lx] %-32s\n", \
+      insn_t wb_insn;
-              (long long)trace_count, tile.Top_Tile_core_ctrl__wb_reg_valid.lo_word(), tile.Top_Tile_core_dpath__wb_reg_pc.lo_word(), \
+      wb_insn.bits = wb_reg_inst;
-              tile.Top_Tile_core_dpath__rf_waddr.lo_word(), tile.Top_Tile_core_dpath__rf_wdata.lo_word(), tile.Top_Tile_core_dpath__rf_wen.lo_word(),
+      std::string wb_disasm = disasm.disassemble(wb_insn);
-              wb_reg_raddr1, wb_reg_rs1, wb_reg_raddr2, wb_reg_rs2, wb_reg_inst, wb_inst_str);
-    }
-
-    if (vcd)
-    {
-      tile.dump(vcdfile, trace_count); // dump all signals to vcd
       
-      #define dump_disasm(inst, name) do { \
+      if (log || (quiet && trace_count % 10000 == 0))
-        insn_t insn; \
+      {
-        insn.bits = inst; \
+        fprintf(logfile, "C: %10lld [%ld] pc=[%011lx] W[r%2ld=%016lx][%ld] R[r%2ld=%016lx] R[r%2ld=%016lx] inst=[%08lx] %-32s\n", \
-        std::string dasm = disasm.disassemble(insn); \
+                (long long)trace_count, tile.Top_Tile_core_ctrl__wb_reg_valid.lo_word(), tile.Top_Tile_core_dpath__wb_reg_pc.lo_word(), \
-        int namelen = strlen(name), pos = 0; \
+                tile.Top_Tile_core_dpath__wb_reg_waddr.lo_word(), tile.Top_Tile_core_dpath__wb_wdata.lo_word(), tile.Top_Tile_core_dpath__wb_wen.lo_word(),
-        char str[1 + dasm.length()*8 + 1 + namelen + 1 + 1]; \
+                wb_reg_raddr1, wb_reg_rs1, wb_reg_raddr2, wb_reg_rs2, wb_reg_inst, wb_disasm.c_str());
-        str[pos++] = 'b'; \
+      }
-        for (size_t i = 0; i < dasm.length()*8; i++) \
-          str[pos++] = ((dasm[i/8] >> (7-(i%8))) & 1) + '0'; \
-        str[pos++] = ' '; \
-        memcpy(str + pos, name, namelen); pos += namelen; \
-        str[pos++] = '\n'; \
-        str[pos] = 0; \
-        fputs(str, vcdfile); \
-      } while(0)
-      dump_disasm(tile.Top_Tile_core_dpath__id_inst.lo_word(), "NDISASM_ID");
-      dump_disasm(ex_reg_inst, "NDISASM_EX");
-      dump_disasm(mem_reg_inst, "NDISASM_MEM");
 
-      dat_dump(vcdfile, dat_t<64>(trace_count), "NCYCLE\n");
+      if (vcd)
+      {
+        wb_disasm.resize(disasm_len, ' ');
+        dat_t<disasm_len*8> disasm_dat;
+        for (size_t i = 0; i < disasm_len; i++)
+          disasm_dat = disasm_dat << 8 | LIT<8>(wb_disasm[i]);
+
+        tile.dump(vcdfile, trace_count);
+        dat_dump(vcdfile, disasm_dat, "NDISASM_WB");
+        dat_dump(vcdfile, dat_t<64>(trace_count), "NCYCLE\n");
+      }
     }
 
-    // delay values from ex stage for trace output on the following cycle
-    wb_reg_inst = mem_reg_inst;
-    wb_reg_raddr1 = mem_reg_raddr1;
-    wb_reg_raddr2 = mem_reg_raddr2;
-    wb_reg_rs1 = mem_reg_rs1;
-    wb_reg_rs2 = mem_reg_rs2;
-
-    mem_reg_inst = ex_reg_inst;
-    mem_reg_raddr1 = (mem_reg_inst >> 22) & 0x1f;
-    mem_reg_raddr2 = (mem_reg_inst >> 17) & 0x1f;
-    mem_reg_rs1 = tile.Top_Tile_core_dpath__ex_reg_rs1.lo_word();
-    mem_reg_rs2 = tile.Top_Tile_core_dpath__ex_reg_rs2.lo_word();
-
-    ex_reg_inst = tile.Top_Tile_core_dpath__id_inst.lo_word();
-
     tile.clock_hi(LIT<1>(0));
     trace_count++;
 

hardfloat

@@ -1 +1 @@
-Subproject commit ada8b49d451176f3d08e3cc08e30ff2659d2803d
+Subproject commit fc09bea89982c4d7d33b6201896aa3b40caba186

riscv-rocket

@@ -1 +1 @@
-Subproject commit 6866daa75f2b99da23d36feab200d8676c177d8d
+Subproject commit 7a225aac9ec81d59d6e161cd9ea554b00b0d0906