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tilelink2: fix a bug in UIntToOH1 triggered if the size was too big

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This commit is contained in:
Wesley W. Terpstra
2016-09-04 21:54:23 -07:00
parent 9f45212c95
commit cf0291061d
3 changed files with 4 additions and 5 deletions
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3
src/main/scala/uncore/tilelink2/Edges.scala
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@@ -12,8 +12,7 @@ class TLEdge(
{ {
def isAligned(address: UInt, lgSize: UInt) = def isAligned(address: UInt, lgSize: UInt) =
if (maxLgSize == 0) Bool(true) else { if (maxLgSize == 0) Bool(true) else {
val ones = UInt((1 << maxLgSize) - 1) val mask = ~(SInt(-1, width=maxLgSize).asUInt << lgSize)(maxLgSize-1, 0)
val mask = (ones << lgSize)(maxLgSize*2-1, maxLgSize)
(address & mask) === UInt(0) (address & mask) === UInt(0)
} }

2
src/main/scala/uncore/tilelink2/Fragmenter.scala
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@@ -139,7 +139,7 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
val maxDownSize = if (alwaysMin) minSize else manager.maxTransfer val maxDownSize = if (alwaysMin) minSize else manager.maxTransfer
def OH1ToUInt(x: UInt) = OHToUInt((x << 1 | UInt(1)) ^ x) def OH1ToUInt(x: UInt) = OHToUInt((x << 1 | UInt(1)) ^ x)
def UIntToOH1(x: UInt, width: Int) = (UInt((1 << width) - 1) << x)(width*2-1, width) def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0)
// First, handle the return path // First, handle the return path
val acknum = RegInit(UInt(0, width = counterBits)) val acknum = RegInit(UInt(0, width = counterBits))

4
src/main/scala/uncore/tilelink2/Narrower.scala
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@@ -26,7 +26,7 @@ class TLNarrower(innerBeatBytes: Int) extends LazyModule
val ratio = innerBeatBytes / outerBeatBytes val ratio = innerBeatBytes / outerBeatBytes
val bce = edge.manager.anySupportAcquire && edge.client.anySupportProbe val bce = edge.manager.anySupportAcquire && edge.client.anySupportProbe
def UIntToOH1(x: UInt, width: Int) = (UInt((1 << width) - 1) << x)(width*2-1, width) def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0)
def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None
def split(in: HasTLData, fire: Bool): (Bool, UInt, UInt) = { def split(in: HasTLData, fire: Bool): (Bool, UInt, UInt) = {
@@ -96,7 +96,7 @@ class TLNarrower(innerBeatBytes: Int) extends LazyModule
out.a.bits.mask := amask out.a.bits.mask := amask
val (dlast, ddata) = merge(out.d.bits, out.d.fire()) val (dlast, ddata) = merge(out.d.bits, out.d.fire())
out.d.ready := in.d.ready out.d.ready := in.d.ready || !dlast
in.d.valid := out.d.valid && dlast in.d.valid := out.d.valid && dlast
in.d.bits := out.d.bits in.d.bits := out.d.bits
in.d.bits.data := ddata in.d.bits.data := ddata