diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala
index b4992a3c..e0db5333 100644
--- a/src/main/scala/coreplex/RocketCoreplex.scala
+++ b/src/main/scala/coreplex/RocketCoreplex.scala
@@ -3,6 +3,7 @@
 package freechips.rocketchip.coreplex
 
 import Chisel._
+import chisel3.experimental.dontTouch
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
@@ -110,9 +111,9 @@ trait HasRocketTilesModuleImp extends LazyModuleImp
 
   // TODO make this less gross and/or support tiles with differently sized reset vectors
   def resetVectorBits: Int = outer.paddrBits
-  val rocket_tile_inputs = Wire(Vec(outer.nRocketTiles, new ClockedRocketTileInputs()(p.alterPartial {
+  val rocket_tile_inputs = dontTouch(Wire(Vec(outer.nRocketTiles, new ClockedRocketTileInputs()(p.alterPartial {
     case SharedMemoryTLEdge => outer.sharedMemoryTLEdge
-  })))
+  })))) // dontTouch keeps constant prop from sucking these signals into the tile
 
   // Unconditionally wire up the non-diplomatic tile inputs
   outer.rocket_tiles.map(_.module).zip(rocket_tile_inputs).foreach { case(tile, wire) =>
@@ -126,7 +127,7 @@ trait HasRocketTilesModuleImp extends LazyModuleImp
   rocket_tile_inputs.zipWithIndex.foreach { case(wire, i) =>
     wire.clock := clock
     wire.reset := reset
-    wire.hartid := UInt(i)
+    wire.hartid := i.U
     wire.reset_vector := global_reset_vector
   }
 }