diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 9d7c6814..67341d42 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -415,7 +415,6 @@ class Top extends Component {
     tl.release_data.bits.header.dst := UFix(0)
     p_rep_data_q.ready := tl.release_data.ready
 
-    tile.io.tilelink.abort <> Queue(tl.abort)
     tile.io.tilelink.grant <> Queue(tl.grant, 1, pipe = true)
     tile.io.tilelink.probe <> Queue(tl.probe)
     il := hl.reset
diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala
index ceb4f263..144d9962 100644
--- a/src/main/scala/fpga.scala
+++ b/src/main/scala/fpga.scala
@@ -68,7 +68,6 @@ class FPGATop extends Component {
     il := hl.reset
     tl.acquire <> Queue(tile.io.tilelink.acquire)
     tl.acquire_data <> Queue(tile.io.tilelink.acquire_data)
-    tile.io.tilelink.abort <> Queue(tl.abort)
     tile.io.tilelink.grant <> Queue(tl.grant)
     tl.grant_ack <> Queue(tile.io.tilelink.grant_ack)
     tile.io.tilelink.probe <> Queue(tl.probe)