riscv/rocket-chip
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coreplex: tidy up interrupt crossings

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This commit is contained in:
Wesley W. Terpstra 2017-10-25 16:13:55 -07:00
parent e30906589f
commit ce2b904b19
2 changed files with 16 additions and 19 deletions
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27
src/main/scala/coreplex/RocketCoreplex.scala
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@ -118,24 +118,21 @@ trait HasRocketTiles extends HasTiles
// NOTE: The order of calls to := matters! They must match how interrupts
// are decoded from rocket.intNode inside the tile.
val asyncIntXbar = LazyModule(new IntXbar).suggestName(tp.name.map(_ + "AsyncIntXbar"))
asyncIntXbar.intnode := debug.intnode // debug
wrapper.intXbar.intnode := wrapper.crossIntAsyncIn() := asyncIntXbar.intnode // 1. always crosses
wrapper.intXbar.intnode := wrapper { IntSyncCrossingSink(3) } := debug.intnode // 1. always async crossign
val periphIntXbar = LazyModule(new IntXbar).suggestName(tp.name.map(_ + "PeriphIntXbar"))
periphIntXbar.intnode := clint.intnode // msip+mtip
periphIntXbar.intnode := plic.intnode // meip
if (tp.core.useVM) periphIntXbar.intnode := plic.intnode // seip
wrapper.intXbar.intnode := wrapper.crossIntIn := periphIntXbar.intnode // 2. conditionally crosses
// 2. clint+plic conditionak crossing
val periphIntNode = SourceCardinality { implicit p => wrapper.intXbar.intnode :=? wrapper.crossIntIn }
periphIntNode := clint.intnode // msip+mtip
periphIntNode := plic.intnode // meip
if (tp.core.useVM) periphIntNode := plic.intnode // seip
val coreIntXbar = LazyModule(new IntXbar).suggestName(tp.name.map(_ + "CoreIntXbar"))
lip.foreach { coreIntXbar.intnode := _ } // lip
wrapper.intXbar.intnode := coreIntXbar.intnode // 3. never crosses
lip.foreach { wrapper.intXbar.intnode := _ } // 3. lip never crosses
wrapper.rocket.intOutputNode.foreach { i => // 4. conditionally crosses
plic.intnode := FlipRendering { implicit p =>
wrapper.crossIntIn := i
}
// From core to PLIC
wrapper.rocket.intOutputNode.foreach { i => // 4. conditional crossing
FlipRendering { implicit p => SourceCardinality { implicit p =>
plic.intnode :=? wrapper.crossIntOut :=? i
} }
}
wrapper

8
src/main/scala/devices/debug/Debug.scala
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@ -393,7 +393,7 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
val dmiXbar = LazyModule (new TLXbar())
val dmOuter = LazyModule( new TLDebugModuleOuter(device))
val intnode = dmOuter.intnode
val intnode: IntSyncOutwardNode = IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode
val dmiInnerNode = TLAsyncCrossingSource()(dmiXbar.node)
@ -402,7 +402,7 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
lazy val module = new LazyModuleImp(this) {
val nComponents = intnode.out.size
val nComponents = dmOuter.intnode.edges.out.size
val io = IO(new Bundle {
val dmi = new DMIIO()(p).flip()
@ -1040,7 +1040,7 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule {
}
val dmOuter = LazyModule(new TLDebugModuleOuterAsync(device)(p))
val dmInner = LazyModule(new TLDebugModuleInnerAsync(device, () => {intnode.edges.out.size})(p))
val dmInner = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size})(p))
val node = dmInner.tlNode
val intnode = dmOuter.intnode
@ -1048,7 +1048,7 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule {
dmInner.dmiNode := dmOuter.dmiInnerNode
lazy val module = new LazyModuleImp(this) {
val nComponents = intnode.out.size
val nComponents = dmOuter.dmOuter.intnode.edges.out.size
val io = IO(new Bundle {
val ctrl = new DebugCtrlBundle(nComponents)