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coreplex: tidy up interrupt crossings

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This commit is contained in:
Wesley W. Terpstra
2017-10-25 16:13:55 -07:00
parent e30906589f
commit ce2b904b19
2 changed files with 16 additions and 19 deletions
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8
src/main/scala/devices/debug/Debug.scala
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@ -393,7 +393,7 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
val dmiXbar = LazyModule (new TLXbar())
val dmOuter = LazyModule( new TLDebugModuleOuter(device))
val intnode = dmOuter.intnode
val intnode: IntSyncOutwardNode = IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode
val dmiInnerNode = TLAsyncCrossingSource()(dmiXbar.node)
@ -402,7 +402,7 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
lazy val module = new LazyModuleImp(this) {
val nComponents = intnode.out.size
val nComponents = dmOuter.intnode.edges.out.size
val io = IO(new Bundle {
val dmi = new DMIIO()(p).flip()
@ -1040,7 +1040,7 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule {
}
val dmOuter = LazyModule(new TLDebugModuleOuterAsync(device)(p))
val dmInner = LazyModule(new TLDebugModuleInnerAsync(device, () => {intnode.edges.out.size})(p))
val dmInner = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size})(p))
val node = dmInner.tlNode
val intnode = dmOuter.intnode
@ -1048,7 +1048,7 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule {
dmInner.dmiNode := dmOuter.dmiInnerNode
lazy val module = new LazyModuleImp(this) {
val nComponents = intnode.out.size
val nComponents = dmOuter.dmOuter.intnode.edges.out.size
val io = IO(new Bundle {
val ctrl = new DebugCtrlBundle(nComponents)